Abstract: Systems and methods to perform a register access are described. A particular method includes receiving a data frame at a bridge element of a plurality of bridge elements in communication with a plurality of server computers. The data frame may include a register access request and may be forwarded from a controlling bridge in communication with the plurality of bridge elements. A register may be accessed and execution of the register access request may be initiated in response to receiving the data frame.

Abstract: Systems and methods to multicast data frames are provided. A particular apparatus includes a plurality of computing nodes and a distributed virtual bridge. The distributed virtual bridge includes a plurality of bridge elements coupled to the plurality of computing nodes. The plurality of bridge elements are configured to forward a copy of a multicast data frame to the plurality of computing nodes using group member information associated with addresses of the plurality of server computers. A controlling bridge coupled to the plurality of bridge elements is configured to communicate the group member information to the plurality of bridge elements.

Abstract: Systems and methods to forward data frames are provided. A particular apparatus may include a plurality of server computers and a distributed virtual bridge. The distributed virtual bridge may include a plurality of bridge elements coupled to the plurality of server computers and configured to forward a data frame between the plurality of server computers. The plurality of bridge elements may further be configured to automatically learn address data associated with the data frame. A controlling bridge may be coupled to the plurality of bridge elements. The controlling bridge may include a global forwarding table that is automatically updated to include the address data and is accessible to the plurality of bridge elements.

Abstract: A method and circuit for implementing end-to-end credit management for enhanced large packet reassembly in an interconnect system, and a design structure on which the subject circuit resides are provided. A transport layer provides buffering and credit control for a super packet received from a source device. A source transport layer sends an End-to-End (ETE) credit request message to a destination transport layer for an outstanding super packet transmission to a destination device. The destination transport layer grants credit to allow at least one source to send a super packet to the destination. The source transport layer fragments the super packet into multiple packets and sends all packets of the super packet only responsive to the credit request being granted by the destination transport layer that is needed to send all packets of the super packet.

Abstract: Systems and methods to forward data frames are described. A particular method may include receiving a data frame at a switch of a plurality of networked switches coupled to a plurality of server computers. The data frame may be forwarded from a controlling bridge coupled to the plurality of networked switches. The data frame may be determined to include management data, and an operating parameter of the switch may be modified.

Abstract: Systems and methods to forward data frames are provided. A particular method may include evaluating address data of a first data frame at a first virtual bridge coupled to a first virtual machine of a first server computer of a plurality of server computers. Based upon the evaluation at the first virtual bridge, the first data frame may be forwarded to a second virtual bridge associated with an adapter that is coupled to the first virtual machine. The address data of the first data frame may be evaluated at the second virtual bridge. Based upon the evaluation, the data frame may be forwarded to a third virtual bridge configured to forward the data frame based upon the address data to a second server computer of the plurality of server computers.

Abstract: A method and circuit for implementing control using a single path in a multiple path interconnect system, and a design structure on which the subject circuit resides are provided. Control TL messages include control information to be transferred between a respective source transport layer of a source interconnect chip and a destination transport layer of a destination interconnect chip. Each transport layer (TL) includes a TL message port identifying a port used to send and receive control TL messages for a pair of source TL and destination TL. The respective TL message port of the pair of source TL and destination TL defines the single path used for control messages.

Abstract: Systems and methods to forward data frames are provided. A particular method may include receiving a data frame at a distributed virtual bridge. The distributed virtual bridge includes a first bridge element coupled to a first server computer and a second bridge element coupled to the first bridge element and to a second server computer. The distributed virtual bridge further includes a controlling bridge coupled to the first bridge element and to the second bridge element. The controlling bridge includes a global forwarding table. The data frame is forwarded from the first bridge element to the second bridge element of the distributed virtual bridge using address data associated with the data frame. A logical network associated with the frame may additionally be used to forward the data frame.

Abstract: Performance counters are provided for virtualized network interfaces of communications networks, while minimizing the use of hardware resources. A virtualized network interface includes physical resources, as well as logical resources. Dedicated performance counters are provided for the physical resources of the virtualized network interface, as well as for logical partitions coupled to that interface, while non-dedicated performance counters are provided for the logical resources. This enables the provision of performance counters for virtualized network interfaces, while minimizing hardware resources consumed by those interfaces.

Abstract: An information processing system is provided which includes a plurality of system resources, and an event queue having a maximum number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.

Abstract: Computer systems with direct updating of cache (e.g., primary L1 cache) memories of a processor, such as a central processing unit (CPU) or graphics processing unit (GPU). Special addresses are reserved for high speed memory. Memory access requests involving these reserved addresses are routed directly to the high speed memory. Memory access requests not involving these reserved addresses are routed to memory external to the processor.

Abstract: Methods and systems for dynamically adjusting credits used to distribute available bus bandwidth among multiple virtual channels, based on the workload of each virtual channel, are provided. Accordingly, for some embodiments, virtual channels with higher workloads relative to other virtual channels may receive a higher allocation of bus bandwidth (more credits).

Abstract: Performance counters are provided for virtualized network interfaces of communications networks, while minimizing the use of hardware resources. A virtualized network interface includes physical resources, as well as logical resources. Dedicated performance counters are provided for the physical resources of the virtualized network interface, as well as for logical partitions coupled to that interface, while non-dedicated performance counters are provided for the logical resources. This enables the provision of performance counters for virtualized network interfaces, while minimizing hardware resources consumed by those interfaces.

Abstract: A processor node of a network is provided which includes one or more processors and a virtualized channel adapter. The virtualized channel adapter is operable to reference a table to determine whether a destination of the communication is supported by the virtualized channel adapter. When the destination is supported for routing via hardware, the virtualized channel adapter is operable to route the communication via hardware to at least one of a physical port and a logical port of the virtualized channel adapter. Otherwise, when the destination is not supported for routing via hardware, the virtualized channel adapter is operable to route the communication via firmware to a virtual port of the virtualized channel adapter. A corresponding method and a recording medium having information recorded thereon for performing such method are also provided herein.

Abstract: Performance counters are provided for virtualized network interfaces of communications networks, while minimizing the use of hardware resources. A virtualized network interface includes physical resources, as well as logical resources. Dedicated performance counters are provided for the physical resources of the virtualized network interface, as well as for logical partitions coupled to that interface, while non-dedicated performance counters are provided for the logical resources. This enables the provision of performance counters for virtualized network interfaces, while minimizing hardware resources consumed by those interfaces.

Abstract: An information processing system is provided which includes a plurality of system resources, and an event queue having a maximum number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.

Abstract: An information processing system is provided which includes a plurality of system resources, and an event queue having a predetermined number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.

Abstract: Methods and systems for dynamically adjusting credits used to distribute available bus bandwidth among multiple virtual channels, based on the workload of each virtual channel, are provided. Accordingly, for some embodiments, virtual channels with higher workloads relative to other virtual channels may receive a higher allocation of bus bandwidth (more credits).

Abstract: An information processing system is provided which includes a plurality of system resources, and an event queue having a maximum number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.

Abstract: A data compression method and compression data structure are provided for a direct access storage device (DASD). The DASD is segmented into a plurality of compression groups. Each of the compression groups has a fixed logical size. A directory table is written within each of the compression groups. Each compression group has at least one compressed data region on which compressed data can be written and an exception region on which compressed data exceptions can be written. The compressed data exceptions include updated compressed data which exceeds an original storage space for corresponding original compressed data.