Patents by Inventor Bruce R. Hancock
Bruce R. Hancock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9596460Abstract: The effects of inter pixel capacitance in a pixilated array may be measured by first resetting all pixels in the array to a first voltage, where a first image is read out, followed by resetting only a subset of pixels in the array to a second voltage, where a second image is read out, where the difference in the first and second images provide information about the inter pixel capacitance. Other embodiments are described and claimed.Type: GrantFiled: June 10, 2013Date of Patent: March 14, 2017Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGYInventors: Suresh Seshadri, David Cole, Roger M. Smith, Bruce R. Hancock
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Patent number: 9294077Abstract: A method and circuit for injecting charge into a circuit node, comprising (a) resetting a capacitor's voltage through a first transistor; (b) after the resetting, pre-charging the capacitor through the first transistor; and (c) after the pre-charging, further charging the capacitor through a second transistor, wherein the second transistor is connected between the capacitor and a circuit node, and the further charging draws charge through the second transistor from the circuit node, thereby injecting charge into the circuit node.Type: GrantFiled: July 24, 2013Date of Patent: March 22, 2016Assignee: California Institute of TechnologyInventor: Bruce R. Hancock
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Publication number: 20150304653Abstract: The effects of inter pixel capacitance in a pixilated array may be measured by first resetting all pixels in the array to a first voltage, where a first image is read out, followed by resetting only a subset of pixels in the array to a second voltage, where a second image is read out, where the difference in the first and second images provide information about the inter pixel capacitance. Other embodiments are described and claimed.Type: ApplicationFiled: June 10, 2013Publication date: October 22, 2015Inventors: Suresh SESHADRI, David COLE, Roger M. SMITH, Bruce R. HANCOCK
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Patent number: 9105548Abstract: A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.Type: GrantFiled: June 22, 2012Date of Patent: August 11, 2015Assignee: California Institute of TechnologyInventors: Thomas J. Cunningham, Bruce R. Hancock, Chao Sun, Todd J. Jones, Matthew R. Dickie, Shouleh Nikzad, Michael E. Hoenk, Christopher J. Wrigley, Kenneth W. Newton, Bedabrata Pain
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Patent number: 8928379Abstract: A latch circuit that uses two interoperating latches. The latch circuit has the beneficial feature that it switches only a single time during a measurement that uses a stair step or ramp function as an input signal in an analog to digital converter. This feature minimizes the amount of power that is consumed in the latch and also minimizes the amount of high frequency noise that is generated by the latch. An application using a plurality of such latch circuits in a parallel decoding ADC for use in an image sensor is given as an example.Type: GrantFiled: February 15, 2013Date of Patent: January 6, 2015Assignee: California Institute of TechnologyInventor: Bruce R. Hancock
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Publication number: 20140027610Abstract: A method and circuit for injecting charge into a circuit node, comprising (a) resetting a capacitor's voltage through a first transistor; (b) after the resetting, pre-charging the capacitor through the first transistor; and (c) after the pre-charging, further charging the capacitor through a second transistor, wherein the second transistor is connected between the capacitor and a circuit node, and the further charging draws charge through the second transistor from the circuit node, thereby injecting charge into the circuit node.Type: ApplicationFiled: July 24, 2013Publication date: January 30, 2014Inventor: Bruce R. Hancock
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Patent number: 8624769Abstract: An analog-to-digital converter (ADC) converts pixel voltages from a CMOS image into a digital output. A voltage ramp generator generates a voltage ramp that has a linear first portion and a non-linear second portion. A digital output generator generates a digital output based on the voltage ramp, the pixel voltages, and comparator output from an array of comparators that compare the voltage ramp to the pixel voltages. A return lookup table linearizes the digital output values.Type: GrantFiled: August 10, 2012Date of Patent: January 7, 2014Assignee: California Institute of TechnologyInventors: Christopher James Wrigley, Bruce R. Hancock, Kenneth W. Newton, Thomas J. Cunningham
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Publication number: 20130214760Abstract: A latch circuit that uses two interoperating latches. The latch circuit has the beneficial feature that it switches only a single time during a measurement that uses a stair step or ramp function as an input signal in an analog to digital converter. This feature minimizes the amount of power that is consumed in the latch and also minimizes the amount of high frequency noise that is generated by the latch. An application using a plurality of such latch circuits in a parallel decoding ADC for use in an image sensor is given as an example.Type: ApplicationFiled: February 15, 2013Publication date: August 22, 2013Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGYInventor: Bruce R. Hancock
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Publication number: 20130175430Abstract: A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.Type: ApplicationFiled: June 22, 2012Publication date: July 11, 2013Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGYInventors: Thomas J. Cunningham, Bruce R. Hancock, Chao Sun, Todd J. Jones, Matthew R. Dickie, Shouleh Nikzad, Michael E. Hoenk, Christopher J. Wrigley, Kenneth W. Newton, Bedabrata Pain
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Patent number: 8481907Abstract: The effects of inter pixel capacitance in a pixilated array may be measured by first resetting all pixels in the array to a first voltage, where a first image is read out, followed by resetting only a subset of pixels in the array to a second voltage, where a second image is read out, where the difference in the first and second images provide information about the inter pixel capacitance. Other embodiments are described and claimed.Type: GrantFiled: January 18, 2008Date of Patent: July 9, 2013Assignee: California Institute of TechnologyInventors: Suresh Seshadri, David Cole, Roger M Smith, Bruce R. Hancock
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Publication number: 20130038482Abstract: An analog-to-digital converter (ADC) converts pixel voltages from a CMOS image into a digital output. A voltage ramp generator generates a voltage ramp that has a linear first portion and a non-linear second portion. A digital output generator generates a digital output based on the voltage ramp, the pixel voltages, and comparator output from an array of comparators that compare the voltage ramp to the pixel voltages. A return lookup table linearizes the digital output values.Type: ApplicationFiled: August 10, 2012Publication date: February 14, 2013Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGYInventors: Christopher James Wrigley, Bruce R. Hancock, Kenneth W. Newton, Thomas J. Cunningham
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Publication number: 20100020099Abstract: The effects of inter pixel capacitance in a pixilated array may be measured by first resetting all pixels in the array to a first voltage, where a first image is read out, followed by resetting only a subset of pixels in the array to a second voltage, where a second image is read out, where the difference in the first and second images provide information about the inter pixel capacitance. Other embodiments are described and claimed.Type: ApplicationFiled: January 18, 2008Publication date: January 28, 2010Applicant: California Institute of TechnologyInventors: Suresh Seshadri, David Cole, Roger M. Smith, Bruce R. Hancock
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Patent number: 7274815Abstract: An apparatus is disclosed for generating a three-dimensional (3-D) image of a scene illuminated by a pulsed light source (e.g. a laser or light-emitting diode). The apparatus, referred to as a phase-sensitive 3-D imaging camera utilizes a two-dimensional (2-D) array of photodetectors to receive light that is reflected or scattered from the scene and processes an electrical output signal from each photodetector in the 2-D array in parallel using multiple modulators, each having inputs of the photodetector output signal and a reference signal, with the reference signal provided to each modulator having a different phase delay. The output from each modulator is provided to a computational unit which can be used to generate intensity and range information for use in generating a 3-D image of the scene. The 3-D camera is capable of generating a 3-D image using a single pulse of light, or alternately can be used to generate subsequent 3-D images with each additional pulse of light.Type: GrantFiled: October 9, 2003Date of Patent: September 25, 2007Assignees: Sandia Corporation, California Institute of TechnologyInventors: Colin L. Smithpeter, Eddie R. Hoover, Bedabrata Pain, Bruce R. Hancock, Robert O. Nellums
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Patent number: 7235771Abstract: A multiple-step reset process and circuit for resetting a voltage stored on a photodiode of an imaging device. A first stage of the reset occurs while a source and a drain of a pixel source-follower transistor are held at ground potential and the photodiode and a gate of the pixel source-follower transistor are charged to an initial reset voltage having potential less that of a supply voltage. A second stage of the reset occurs after the initial reset voltage is stored on the photodiode and the gate of the pixel source-follower transistor and the source and drain voltages of the pixel source-follower transistor are released from ground potential thereby allowing the source and drain voltages of the pixel source-follower transistor to assume ordinary values above ground potential and resulting in a capacitive feed-through effect that increases the voltage on the photodiode to a value greater than the initial reset voltage.Type: GrantFiled: July 27, 2005Date of Patent: June 26, 2007Assignee: California Institute of TechnologyInventors: Bedabrata Pain, Thomas J. Cunningham, Bruce R. Hancock
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Patent number: 5094974Abstract: For the growth of strain-layer materials and high quality single and multiple quantum wells, the instantaneous control of growth front stoichiometry is critical. The process of the invention adjusts the offset or phase of MBE control shutters to program the instantaneous arrival or flux rate of In and As.sub.4 reactants to grow InAs. The interrupted growth of first In, then As.sub.4, is also a key feature.Type: GrantFiled: February 28, 1990Date of Patent: March 10, 1992Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Frank J. Grunthaner, John K. Liu, Bruce R. Hancock
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Patent number: 5091335Abstract: III-V films are grown on large automatically perfect terraces of III-V substrates which have a different lattice constant, with temperature and Group II and V arrival rates chosen to give a Group III element stable surface. The growth is pulsed to inhibit Group III metal accumulation to low temperature, and to permit the film to relax to equilibrium. The method of the invention 1) minimizes starting step density on sample surface; 2) deposits InAs and GaAs using an interrupted growth mode (0.25 to 2 mono-layers at a time); 3) maintains the instantaneous surface stoichiometry during growth (As-stable for GaAs, In-stable for InAs); and 4) uses time-resolved RHEED to achieve aspects (1)-14 (3).Type: GrantFiled: March 30, 1990Date of Patent: February 25, 1992Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Frank J. Grunthaner, John K. Liu, Bruce R. Hancock