Abstract: In one embodiment the present invention includes a circuit for automatically adjusting an output of an audio device. The circuit includes a memory circuit, a detector circuit, a control circuit, and an output circuit. The memory circuit stores configuration information. The detector circuit detects environment information related to an environment in which the apparatus is present. The control circuit selects selected configuration information from the memory circuit according to the environment information detected by the detector circuit. The output circuit receives an input audio signal and the selected configuration information, modifies the input audio signal according to the selected configuration information, and generates an output audio signal corresponding to the input audio signal as modified according to the selected configuration information.

Abstract: In one embodiment the present invention includes a circuit for automatically adjusting an output of an audio device. The circuit includes a memory circuit, a detector circuit, a control circuit, and an output circuit. The memory circuit stores configuration information. The detector circuit detects environment information related to an environment in which the apparatus is present. The control circuit selects selected configuration information from the memory circuit according to the environment information detected by the detector circuit. The output circuit receives an input audio signal and the selected configuration information, modifies the input audio signal according to the selected configuration information, and generates an output audio signal corresponding to the input audio signal as modified according to the selected configuration information.

Abstract: A phase locked loop circuit may be utilized as a low jitter clock regenerator in order to generate an extremely stable low jitter signal which is to a large extent immune from input phase and frequency noise. The slaving clock generates an output at a fixed phase relationship to a reference input. The clock regenerator is advantageously implemented by a logic gate type phase detector connected to a multi-stage loop filter. The loop filter output is connected to a phase correction circuit whose output is mixed with the loop filter output to provide a control input to a voltage controlled oscillator. The voltage controlled oscillator output may be provided directly, or through a frequency divider, to a feed-back input of the phase detector.