Patents by Inventor Bruce Ratcliff
Bruce Ratcliff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11979459Abstract: The embodiments herein describe configuring a data device that enables communication between a host and a shared network adapter. The data device can include data connections between the host and the shared network adapter. The data device can have both control queues in a control plane and data queues in a data plane. The control queues can be activated first in order to issue control commands to configure the data plane in the shared network adapter.Type: GrantFiled: October 12, 2023Date of Patent: May 7, 2024Assignee: International Business Machines CorporationInventors: Bruce Ratcliff, Dan Vangor, Stephen R. Valley, Margaret Dubowsky, Francis Gassert, Jerry Stevens, Richard P. Tarcza, Patricia G. Driever
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Patent number: 11093362Abstract: In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.Type: GrantFiled: June 12, 2019Date of Patent: August 17, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Bruce Ratcliff
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Patent number: 11086748Abstract: In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.Type: GrantFiled: June 12, 2019Date of Patent: August 10, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Bruce Ratcliff
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Patent number: 10949097Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.Type: GrantFiled: November 13, 2019Date of Patent: March 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward W. Chencinski, Bruce Ratcliff, Eric N. Lais, Michael James Becht, Matthias Klein
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Publication number: 20200081627Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.Type: ApplicationFiled: November 13, 2019Publication date: March 12, 2020Inventors: Edward W. Chencinski, Bruce Ratcliff, Eric N. Lais, Michael James Becht, Matthias Klein
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Patent number: 10552054Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.Type: GrantFiled: July 2, 2018Date of Patent: February 4, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward W. Chencinski, Bruce Ratcliff, Eric N. Lais, Michael James Becht, Matthias Klein
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Publication number: 20200004433Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.Type: ApplicationFiled: July 2, 2018Publication date: January 2, 2020Inventors: Edward W. Chencinski, Bruce Ratcliff, Eric N. Lais, Michael James Becht, Matthias Klein
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Publication number: 20190294520Abstract: In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.Type: ApplicationFiled: June 12, 2019Publication date: September 26, 2019Inventor: Bruce Ratcliff
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Publication number: 20190294521Abstract: In one example implementation, a computer-implemented method includes receiving, at a parallel processor complex, a task to be executed by the parallel processor complex. The parallel processor complex includes a trace processor and a plurality of task execution processors, each of the plurality of task execution processors having a plurality of trace buffers associated exclusively therewith. The method further includes creating, by the trace processor, a trace entry by allocating an element from a shared queue. The method further includes loading, by the trace processor, the trace entry into a common trace buffer. The method further includes loading, by the trace processor, the trace entry into one of the plurality of trace buffers based at least in part on an interface identifier and a queue pair index record. The interface identifier identifies the one of the plurality of task execution processors with which the trace entry is associated.Type: ApplicationFiled: June 12, 2019Publication date: September 26, 2019Inventor: Bruce Ratcliff
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Patent number: 10423511Abstract: Examples of techniques for packet flow tracing in a parallel processor complex are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include receiving, at the parallel processor complex, a task to be executed by the parallel processor complex, wherein the parallel processor complex comprises a trace processor and a plurality of task execution processors; creating, by the trace processor, a trace entry by allocating an element from a shared queue; loading, by the trace processor, the trace entry into a common trace buffer; and loading, by the trace processor, the trace entry into a host interface/queue pair index trace buffer.Type: GrantFiled: November 29, 2016Date of Patent: September 24, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Bruce Ratcliff
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Patent number: 10417109Abstract: Examples of techniques for packet flow tracing in a parallel processor complex are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include receiving, at the parallel processor complex, a task to be executed by the parallel processor complex, wherein the parallel processor complex comprises a trace processor and a plurality of task execution processors; creating, by the trace processor, a trace entry by allocating an element from a shared queue; loading, by the trace processor, the trace entry into a common trace buffer; and loading, by the trace processor, the trace entry into a host interface/queue pair index trace buffer.Type: GrantFiled: February 24, 2017Date of Patent: September 17, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Bruce Ratcliff
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Patent number: 10164868Abstract: A physical host executes a virtual machine monitor (VMM) that instantiates a source virtual machine (VM). In response to the VMM receiving from the source VM a packet specifying a first destination address of a destination VM and a second destination address of a default gateway, the VMM determines whether the packet can be communicated to the destination VM without the packet being routed by the default gateway. In response to the VMM determining that the packet can be communicated to the destination VM without the packet being routed by the default gateway, the VMM forwards the packet to the destination VM such that the packet bypasses routing by the default gateway.Type: GrantFiled: April 26, 2012Date of Patent: December 25, 2018Assignee: International Business Machines CorporationInventors: Robert Cowart, David Hadas, Daniel J. Martin, Bruce Ratcliff, Renato Recio
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Patent number: 10142218Abstract: A physical host executes a virtual machine monitor (VMM) that instantiates a source virtual machine (VM). In response to the VMM receiving from the source VM a packet specifying a first destination address of a destination VM and a second destination address of a default gateway, the VMM determines whether the packet can be communicated to the destination VM without the packet being routed by the default gateway. In response to the VMM determining that the packet can be communicated to the destination VM without the packet being routed by the default gateway, the VMM forwards the packet to the destination VM such that the packet bypasses routing by the default gateway.Type: GrantFiled: January 14, 2011Date of Patent: November 27, 2018Assignee: International Business Machines CorporationInventors: Robert Cowart, David Hadas, Daniel J. Martin, Bruce Ratcliff, Renato Recio
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Patent number: 10097508Abstract: Facilitating communications within a processing environment. Inbound traffic and outbound traffic on one or more virtual interfaces of the processing environment are monitored for a predefined amount of time. Based on the monitoring, a determination is made as to whether for a selected component of a virtual interface of the one or more virtual interfaces an inbound frame has been received but an outbound frame has not been transmitted for the predetermined amount of time. Based on determining that the inbound frame has been received but the outbound frame has not been transmitted, a generated outbound frame is forwarded to cause address registration information for the virtual interface to be refreshed.Type: GrantFiled: January 11, 2017Date of Patent: October 9, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey D. Haggar, Bruce Ratcliff, Benjamin T. Rau, Jerry W. Stevens
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Patent number: 10091083Abstract: Facilitating communications within a processing environment. Inbound traffic and outbound traffic on one or more virtual interfaces of the processing environment are monitored for a predefined amount of time. Based on the monitoring, a determination is made as to whether for a selected component of a virtual interface of the one or more virtual interfaces an inbound frame has been received but an outbound frame has not been transmitted for the predetermined amount of time. Based on determining that the inbound frame has been received but the outbound frame has not been transmitted, a generated outbound frame is forwarded to cause address registration information for the virtual interface to be refreshed.Type: GrantFiled: January 11, 2017Date of Patent: October 2, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey D. Haggar, Bruce Ratcliff, Benjamin T. Rau, Jerry W. Stevens
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Publication number: 20180152368Abstract: Examples of techniques for packet flow tracing in a parallel processor complex are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include receiving, at the parallel processor complex, a task to be executed by the parallel processor complex, wherein the parallel processor complex comprises a trace processor and a plurality of task execution processors; creating, by the trace processor, a trace entry by allocating an element from a shared queue; loading, by the trace processor, the trace entry into a common trace buffer; and loading, by the trace processor, the trace entry into a host interface/queue pair index trace buffer.Type: ApplicationFiled: February 24, 2017Publication date: May 31, 2018Inventor: Bruce Ratcliff
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Publication number: 20180150374Abstract: Examples of techniques for packet flow tracing in a parallel processor complex are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include receiving, at the parallel processor complex, a task to be executed by the parallel processor complex, wherein the parallel processor complex comprises a trace processor and a plurality of task execution processors; creating, by the trace processor, a trace entry by allocating an element from a shared queue; loading, by the trace processor, the trace entry into a common trace buffer; and loading, by the trace processor, the trace entry into a host interface/queue pair index trace buffer.Type: ApplicationFiled: November 29, 2016Publication date: May 31, 2018Inventor: Bruce Ratcliff
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Patent number: 9667593Abstract: Facilitating communications within a processing environment. Inbound traffic and outbound traffic on one or more virtual interfaces of the processing environment are monitored for a predefined amount of time. Based on the monitoring, a determination is made as to whether for a selected component of a virtual interface of the one or more virtual interfaces an inbound frame has been received but an outbound frame has not been transmitted for the predetermined amount of time. Based on determining that the inbound frame has been received but the outbound frame has not been transmitted, a generated outbound frame is forwarded to cause address registration information for the virtual interface to be refreshed.Type: GrantFiled: May 12, 2016Date of Patent: May 30, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey D. Haggar, Bruce Ratcliff, Benjamin T. Rau, Jerry W. Stevens
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Publication number: 20170141985Abstract: Facilitating communications within a processing environment. Inbound traffic and outbound traffic on one or more virtual interfaces of the processing environment are monitored for a predefined amount of time. Based on the monitoring, a determination is made as to whether for a selected component of a virtual interface of the one or more virtual interfaces an inbound frame has been received but an outbound frame has not been transmitted for the predetermined amount of time. Based on determining that the inbound frame has been received but the outbound frame has not been transmitted, a generated outbound frame is forwarded to cause address registration information for the virtual interface to be refreshed.Type: ApplicationFiled: January 11, 2017Publication date: May 18, 2017Inventors: Jeffrey D. HAGGAR, Bruce RATCLIFF, Benjamin T. RAU, Jerry W. STEVENS
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Publication number: 20170126620Abstract: Facilitating communications within a processing environment. Inbound traffic and outbound traffic on one or more virtual interfaces of the processing environment are monitored for a predefined amount of time. Based on the monitoring, a determination is made as to whether for a selected component of a virtual interface of the one or more virtual interfaces an inbound frame has been received but an outbound frame has not been transmitted for the predetermined amount of time. Based on determining that the inbound frame has been received but the outbound frame has not been transmitted, a generated outbound frame is forwarded to cause address registration information for the virtual interface to be refreshed.Type: ApplicationFiled: January 11, 2017Publication date: May 4, 2017Inventors: Jeffrey D. HAGGAR, Bruce RATCLIFF, Benjamin T. RAU, Jerry W. STEVENS