Abstract: A method of fabricating a conductive metal oxide gate ferroelectric memory transistor includes forming an oxide layer a substrate and removing the oxide layer in a gate area; depositing a conductive metal oxide layer on the oxide layer and on the exposed gate area; depositing a titanium layer on the metal oxide layer; patterning and etching the titanium layer and the metal oxide layer to remove the titanium layer and the metal oxide layer from the substrate except in the gate area; depositing, patterning and etching an oxide layer to form a gate trench; depositing and etching a barrier insulator layer to form a sidewall barrier in the gate trench; removing the titanium layer from the gate area; depositing, smoothing and annealing a ferroelectric layer in the gate trench; depositing, patterning and etching a top electrode; and completing the conductive metal oxide gate ferroelectric memory transistor.

Abstract: A method for densifying sol-gel films to form microlens structures includes preparing a sol-gel precursor, having at least one solvent therein. The sol-gel precursor is spin coated onto a wafer to form a sol-gel film thereon. The wafer and sol-gel film are hot plate baked at a temperature less than 200° C. to remove at least some of the solvent. The baked, wafer and spin-coated sol-gel film are treated with an oxygen plasma treatment to remove any remaining solvent and to densify the sol-gel film. The spin coating, hot plate baking and treating steps may be repeated as required. A microlens is formed from the densified sol-gel film.

Abstract: A method of forming a microlens array includes preparing a substrate; fabricating a photosensitive array on the substrate; depositing a layer of lens material on the photosensitive array; depositing and patterning photoresist on the lens material, wherein patterning includes forming a photoresist region having a solid curved upper surface and a substantially rectangular base on the lens material layer; developing the photoresist; reflowing the photoresist; and processing the lens material for form a microlens array.

Abstract: A method of etching a top electrode/ferroelectric stack using an etch stop layer includes forming a first layer of a first dielectric material on a substrate; forming a bottom electrode in the first layer of a first dielectric material; depositing an etch stop layer on the first layer of the first dielectric material and the bottom electrode, including forming a hole therein; depositing a layer of ferroelectric material and depositing top electrode material on the ferroelectric material to form a top electrode/ferroelectric stack; stack etching the top electrode and ferroelectric material; depositing a layer of a second dielectric material encapsulating the top electrode and ferroelectric material; etching the layer of the second dielectric material to form a sidewall about the top electrode and ferroelectric material; and depositing a second and third layers of the first dielectric material.

Abstract: A two dimensional vernier is provided along with a method of fabrication. The two dimensional vernier has a reference array patterned into a substrate, or a material overlying the substrate. An active array is patterned into photoresist overlying the substrate or the material. Both the reference array and the active array each comprise a two dimensional array of shapes. A difference between a combination of size or spacing of the shapes in each array determines vernier resolution. Vernier range is determined by a combination of vernier resolution and an integer related to a total number of shapes along a given axis. The two dimensional vernier allows an operator to readily measure the misalignment of a pattern to be processed relative to a previous pattern in two dimensions using a microscope. The two dimensional vernier reduces, or eliminates, repositioning of the microscope to determine both x-axis misalignment and y-axis misalignment.

Abstract: A method of selectively etching a three-layer structure consisting of SiO2, In2O3, and titanium, includes etching the SiO2, stopping at the titanium layer, using C3F8 in a range of between about 10 sccm to 30 sccm; argon in a range of between about 20 sccm to 40 sccm, using an RF source in a range of between about 1000 watts to 3000 watts and an RF bias in a range of between about 400 watts to 800 watts at a pressure in a range of between about 2 mtorr to 6 mtorr; and etching the titanium, stopping at the In2O3 layer, using BCl in a range of between about 10 sccm to 50 sccm; chlorine in a range of between about 40 sccm to 80 sccm, a Tcp in a range of between about 200 watts to 500 watts at an RF bias in a range of between about 100 watts to 200 watts at a pressure in a range of between about 4 mtorr to 8 mtorr.

Abstract: A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture could increase the etch rate for the silicon nitride while reducing the etch rate for the conductive oxide, resulting in improving etch selectivity. The disclosed selective etch process is well suited for ferroelectric memory device fabrication using conductive oxide/ferroelectric interface having silicon nitride as the encapsulated material for the ferroelectric.

Abstract: A method of forming a microlens structure using a patternable lens material is provided. An organic-inorganic hybrid polymer comprising titanium dioxide is exposed to light using a defocused mask image and then developed to produce a lens-shaped region.

Abstract: A method of etching a noble metal top electrode on a ferroelectric layer while preserving the ferroelectric properties of the ferroelectric layer and removing etching residue includes preparing a substrate; depositing a barrier layer on the substrate; depositing a bottom electrode layer on the barrier layer; depositing a ferroelectric layer on the bottom electrode layer; depositing a noble metal top electrode layer on the ferroelectric layer; depositing an adhesion layer on the top electrode layer; depositing a hard mask layer on the adhesion layer; patterning the hard mask; etching the noble metal top electrode layer in an initial etching step at a predetermined RF bias power, which produces etching residue; and over etching the noble metal top electrode layer and ferroelectric layer at an RF bias power lower than that of the predetermined RF bias power to remove etching residue from the initial etching step.

Abstract: A methods of forming a microlens structure are provided. An embodiment of the method comprises exposing a photoresist layer a predetermined focus and exposure to sensitize a lens-shaped region within the photoresist layer. The photoresist layer is then developed to form a lens-shaped region within the photoresist layer. The lens-shaped region may then be transferred to an underlying material. The underlying material may be a transparent material within which a lens is subsequently formed. Alternatively, the underlying material is a lens material that will form the microlens once the lens-shaped region is transferred.

Abstract: A one-mask etching method for use with a PCMO-containing RRAM to reduce stack side-wall residuals, includes preparing a substrate, taken from the group of substrates consisting of silicon, silicon dioxide and polysilicon; depositing a bottom electrode on the substrate; depositing a PCMO layer on the bottom electrode; depositing a top electrode on the PCMO layer; depositing a hard mask on the top electrode; depositing and patterning a photoresist layer on the hard mask; etching the hard mask; etching the top electrode using a first etching process having an etching atmosphere consisting of Ar, O2, and Cl2; etching the PCMO layer using an etching process taken from the group of etching processes consisting of the first etching process and a second etching process having an etching atmosphere consisting of Ar and O2. etching the bottom electrode using the first etching process; and completing the RRAM device.

Abstract: Methods of forming depositing a ferroelectric thin film, such as PGO, by preparing a substrate with an upper surface of silicon, silicon oxide, or a high-k material, such as hafnium oxide, zirconium oxide, aluminum oxide, and lanthanum oxide, depositing an indium oxide film over the substrate, and then depositing the ferroelectric film using MOCVD.

Abstract: An ultra-shallow surface channel MOS transistor and method for fabricating the same have been provided. The method comprises: forming CMOS source and drain regions, and an intervening well region; depositing a surface channel on the surface overlying the well region; forming a high-k dielectric overlying the surface channel; and, forming a gate electrode overlying the high-k dielectric. Typically, the surface channel is a metal oxide, and may be one of the following materials: indium oxide (In2O3), ZnO, RuO, ITO, or LaX-1SrXCoO3. In some aspects, the method further comprises: depositing a placeholder material overlying the surface channel; and, etching the placeholder material to form a gate region overlying the surface channel. In one aspect, the high-k dielectric is deposited prior to the deposition of the placeholder material. Alternately, the high-k dielectric is deposited following the etching of the placeholder material.

Abstract: A two dimensional vernier is provided along with a method of fabrication. The two dimensional vernier has a reference array patterned into a substrate, or a material overlying the substrate. An active array is patterned into photoresist overlying the substrate or the material. Both the reference array and the active array each comprise a two dimensional array of shapes. A difference between a combination of size or spacing of the shapes in each array determines vernier resolution. Vernier range is determined by a combination of vernier resolution and an integer related to a total number of shapes along a given axis. The two dimensional vernier allows an operator to readily measure the misalignment of a pattern to be processed relative to a previous pattern in two dimensions using a microscope. The two dimensional vernier reduces, or eliminates, repositioning of the microscope to determine both x-axis misalignment and y-axis misalignment.

Abstract: A method of selective etching a metal oxide layer for fabrication of a ferroelectric device includes preparing a silicon substrate, including forming an oxide layer thereon; depositing a layer of metal or metal oxide thin film on the substrate; patterning and selectively etching the metal or metal oxide thin film without substantially over etching into the underlying oxide layer; depositing a layer of ferroelectric material; depositing a top electrode on the ferroelectric material; and completing the ferroelectric device.

Abstract: A method of selectively depositing a ferroelectric thin film on an indium-containing substrate in a ferroelectric device includes preparing a silicon substrate; depositing an indium-containing thin film on the substrate; patterning the indium containing thin film; annealing the structure; selectively depositing a ferroelectric layer by MOCVD; annealing the structure; and completing the ferroelectric device.