Abstract: Cross-coupling of switched-capacitor output common-mode feedback capacitors in dynamic residue amplifiers is provided via a cross-coupled amplifier, comprising: a current source connected to a first node; a feedback capacitor connected to the first node and a second node; a feedback resistor connected between the second node and ground; an amplifier having an input connected to the second node; a gain transistor having: a drain connected to the first node; a source connected to ground; and a gate connected to an output of the amplifier; and a load capacitor connected to the first node and ground.

Abstract: An analog-to-digital (ADC) circuit is disclosed that includes a first stage, a first amplifier, and a second amplifier. The first stage includes signal processing circuitry, and is configured to receive a differential input signal and generate a differential residue voltage signal on differential output nodes of the first stage. The first amplifier includes first amplifier circuitry. The first amplifier is electrically connected to the differential output nodes of the first stage, and configured to receive the differential residue voltage signal, and generate a first differential voltage signal from the differential residue voltage signal. The second amplifier includes second amplifier circuitry. The second amplifier is electrically connected to differential output nodes of the first amplifier, and configured to receive the first differential voltage signal, and generate a second differential voltage signal from the first differential voltage signal.

Abstract: An amplifier comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first transistor, a second transistor, and an output node. The first capacitor is electrically connected between a first power supply node and a first node, the second capacitor is electrically connected between the first node and a second node, the third capacitor is electrically connected between a second power supply node and a third node, and the fourth capacitor is electrically connected between the third node and a fourth node. The first transistor has a gate node electrically connected to the second node, and the second transistor has a gate node electrically connected to the fourth node. The output node is selectively connected to the first transistor and the second transistor. The first node and the third node are configured to be selectively electrically connected to a voltage node and a common voltage node.

Abstract: Apparatus and associated methods relate to an input buffer having a source follower connected in series with a push-pull driver to generate a shield reference node that provides conductive traces extending from the shield reference node and disposed between gate traces of the input buffer and a corresponding nearest reference potential node. In an illustrative example, the push-pull driver and the source follower may be capacitively coupled, via the gate traces, to receive an input signal from an input node. In some examples, the shield reference node may also include conductive traces disposed between the input node and/or the gate traces and a corresponding nearest reference potential node such that parts of parasitic capacitances in the input buffer may be shielded. Accordingly, the bandwidth of the input buffer may be advantageously improved. The high frequency return loss (S11) may also be improved accordingly.

Abstract: A signal buffer is disclosed. The signal buffer may include one or more bias signal generators to bias one or more transistors. The bias signal generators may generate power supply compensated or ground compensated bias signals. The bias signal generators may include a capacitor to provide a high frequency signal path.

Abstract: An apparatus and method for sampling an analog signal with analog-to-digital converters (ADCs) is disclosed. The ADCs may be separated into a group of interleaved ADCs and a spare ADC. The interleaved ADCs can sample the analog signal according to an interleaving sequence. An interleaved ADC controller can monitor the inactivity of the spare ADC and can replace one of the interleaved ADCs in the interleaving sequence with the spare ADC based on the inactivity.

Abstract: An integrated circuit is described. The integrated circuit comprises an analog-to-digital converter circuit configured to receive an input signal at an input and generate an output signal at an output; and a monitor circuit coupled to the output of the analog-to-digital converter circuit, the monitor circuit configured to receive the output signal and to generate integration coefficients for the analog-to-digital converter circuit; wherein the integration coefficients are dynamically generated based upon signal characteristics of the output signal generated by the analog-to-digital converter circuit. A method of receiving data in an integrated circuit is also described.

Abstract: An analog-to-digital converter (ADC) circuit (400) and method of operation are disclosed. In some aspects, the ADC circuit (400) may include a plurality of channels (500), a gain calibration circuit (420), and a time-skew calibration circuit (430). Each of the plurality of channels (500) may include an ADC (520), a switch (510) configured to provide a differential input signal to the ADC (520), a calibration device (530), a multiplier (540), and a pseudorandom bit sequence (PRBS) circuit (550) to provide a pseudorandom number (PN) to the switch (510), to the calibration device (530), and to the multiplier (540). In some embodiments, the calibration device (530) may include first and second offset calibration circuits (531-532) coupled in parallel between a de-multiplexer (D1) and a multiplexer (M1) that alternately route signals to the first and second offset calibration circuits (531-532) based on the pseudorandom number (PN).

Abstract: Apparatus and associated methods relate to modulating polarity on sample outputs from a time-interleaved analog-to-digital converter (TIADC) as an input to a time skew extractor in a clock skew calibration control loop. In an illustrative example, a multiplier-mixer may impart a polarity change to every other data sample transmitted between the TIADC and the time skew extractor. In some examples, a multiplexer may select between the polarity modulated samples and non-polarity modulated samples before the multiplier-mixer. Selection between the polarity modulated samples and the non-polarity modulated samples may be based on, for example, determination of specific frequency bands of an analog input signal. Various embodiments may improve convergence of clock skew calibration control loops for analog input signals sampled with a TIADC near a Nyquist frequency.

Abstract: An integrated circuit is described. The integrated circuit comprises a first portion having programmable resources; a second portion having hardened circuits including an analog-to-digital converter circuit configured to receive an input signal and generate an output signal; and a monitor circuit configured to receive an output signal generated by the analog-to-digital converter circuit; wherein the monitor circuit is configurable to control a calibration of the analog-to-digital converter circuit based upon signal characteristics of the output signal generated by the analog-to-digital converter circuit. A method of receiving data in an integrated circuit is also described.

Abstract: An example apparatus includes a first transistor coupled between a supply node and a first node, a current mirror having a first side and a second side, and a second transistor coupled between the first node and the first side of the current mirror. The input buffer further includes a third transistor coupled between the first node and the second side of the current mirror, and a first capacitor coupled between a source and a drain of the second transistor.

Abstract: Examples of the present disclosure provide out-of-range voltage detection and protection in integrated circuits (ICs). In some examples, an IC includes an envelope detector, a comparator, and a switch. The envelope detector is configured to generate an envelope signal of a signal and output the envelope signal on an output node of the envelope detector. A first input node of the comparator is coupled to the output node of the envelope detector. The comparator is configured to compare respective signals provided on the first and second input nodes of the comparator and generate a comparison signal in response to the comparison. The comparator is further configured to output the comparison signal on the output node of the comparator. The switch is connected between a protected node and a protection node and is configured to be selectively opened or closed based, at least in part, on the comparison signal.

Abstract: An example apparatus for analog-to-digital conversion includes a plurality of channels each including an analog-to-digital converter (ADC), a switch configured to couple a differential input to the ADC, a first offset calibration circuit coupled to an output of the ADC, a multiplier coupled to an output of the first offset calibration circuit, a second offset calibration circuit coupled to an output of the multiplier, and a pseudorandom bit sequence (PRBS) generator coupled to the switch and the multiplier. The apparatus further includes a gain calibration circuit coupled to an output of the second offset calibration circuit in each of the plurality of channels; and a time-skew calibration circuit coupled to an output of the gain calibration circuit.

Abstract: An example time-skew calibration circuit includes a plurality of first circuits, each including a first accumulator and a second accumulator. The time-skew calibration circuit further includes a plurality of second circuits, each including a first adder coupled to outputs of the first accumulator and the second accumulator, and a first subtractor coupled to the outputs of the first accumulator and the second accumulator. The time-skew calibration circuit further includes a decision circuit configured to combine an output of the first adder and an output of the first subtractor.

Abstract: In an example, an input buffer includes: first buffer circuit having an output, a first voltage control node, and a second voltage control node; a first transistor having a gate coupled to the output of the first buffer circuit, a drain, and a source; a second buffer circuit having an input coupled to a reference voltage and an output coupled to the source of the first transistor; and a first current source having a reference output coupled to the drain of the first transistor, a first output coupled to the first voltage control node of the first buffer circuit, and a second output coupled to the second voltage control node of the second buffer circuit.

Abstract: A time-skew adjustment circuit includes an input to receive a series of samples of an input signal from a plurality of channels of an interleaved ADC. A first subtractor calculates distances between consecutive samples in the received series of samples, and a plurality of average circuit code and a plurality of memory banks to calculate a plurality of first average distance, each corresponding to an average of the distance between consecutive samples from a respective pair of channels of the interleaved ADC. Time-skew detection circuitry calculates respective time skews between each of the pairs of channels by comparing each of the first average distances with an average of the distances between consecutive samples from the plurality of channels. Divergence control circuitry determines an accuracy of the time skews based at least in part on the first average distances and a Nyquist zone associated with the input signal.

Abstract: An example capacitive digital-to-analog converter (CDAC) includes: a first plurality of capacitors consisting of M?1 capacitors, where M is an integer greater than one, the first plurality of capacitors including top plates coupled to a first node; a second plurality of capacitors consisting of M?1 capacitors, the second plurality of capacitors including top plates coupled to a second node; a first plurality of switches consisting of M?1 switches coupled to bottom plates of the respective M?1 capacitors of the first plurality of capacitors, the first plurality of switches further coupled to a third node providing a supply voltage and a fourth node providing a ground voltage; a second plurality of switches consisting of M?1 switches coupled to bottom plates of the respective M?1 capacitors of the second plurality of capacitors, the second plurality of switches coupled to the third node and the fourth node; and a control circuit including an input consisting of M bits for receiving an M bit code and an output c

Abstract: An analog to digital converter (ADC) circuit includes a first stage for converting a first analog voltage signal to a first digital signal including a first portion of a digital output signal representing the first analog voltage signal, and generate a first residue voltage based on the first analog voltage signal and the first digital signal. A first amplifier control unit generates a first amplifier start signal based on a second stage ready signal indicating that a second stage is ready to process a second analog voltage signal. In response to the second stage ready signal, a first amplifier generates the second analog voltage signal based on the first residue voltage. The second stage is configured to generate the second stage ready signal, receive the second analog voltage signal, and convert the second analog voltage signal to a second digital signal including a second portion of the digital output signal.