Abstract: The invention relates to a multiplier circuit which is constructed from two multiplier cells according to the prior art. The disadvantage of different signal transit times in the emitter followers and the differential stages for the two input signals to be treated identically is overcome by arranging the transmission paths symmetrically. The limiting frequency of the arrangement according to the invention is no longer limited by the phase error, but solely by the switching time of the bipolar transistors employed, and is therefore higher than in a multiplier circuit according to the prior art. For all frequencies below the limiting frequency, given a phase difference of 90.degree. the output signal lies exactly in the middle of the modulation range.