Patents by Inventor Bruno Werner Garlepp
Bruno Werner Garlepp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8296540Abstract: A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes tuning circuitry within the slave device such that the performance of the memory system is improved.Type: GrantFiled: February 25, 2008Date of Patent: October 23, 2012Assignee: Rambus Inc.Inventors: Bruno Werner Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos, Richard M. Barth, Paul G. Davis, Ely K. Tsern
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Publication number: 20080162759Abstract: A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.Type: ApplicationFiled: February 25, 2008Publication date: July 3, 2008Applicant: RAMBUS INC.Inventors: Bruno Werner Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos, Richard M. Barth, Paul G. Davis, Ely K. Tsern
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Patent number: 7337294Abstract: A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.Type: GrantFiled: December 11, 2006Date of Patent: February 26, 2008Assignee: Rambus Inc.Inventors: Bruno Werner Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos, Richard M. Barth, Paul G. Davis, Ely K. Tsern
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Patent number: 7308044Abstract: A technique for receiving differential multi-PAM signals is disclosed. In one particular exemplary embodiment, the technique may be realized as a differential multi-PAM extractor circuit. In this particular exemplary embodiment, the differential multi-PAM extractor circuit comprises an upper LSB sampler circuit configured to receive a differential multi-PAM input signal and a first differential reference signal, and to generate a first differential sampled output signal. The differential multi-PAM extractor circuit also comprises a lower LSB sampler circuit configured to receive the differential multi-PAM input signal and a second differential reference signal, and to generate a second differential sampled output signal.Type: GrantFiled: September 30, 2003Date of Patent: December 11, 2007Assignee: Rambus IncInventors: Jared LeVan Zerbe, Grace Tsang, Mark Horowitz, Bruno Werner Garlepp, Carl William Werner
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Patent number: 7149856Abstract: A method and apparatus for adjusting the performance of a memory system is provided. A memory control device comprises a master device including a frequency detector, a memory channel, and a memory device coupled to the master device via the memory channel. The memory device includes a decoder designed to receive a control signal from the master device. A clock recovery and alignment circuit receives the control signal from the decoder and adjusts the operating frequency of the memory device in response to the control signal.Type: GrantFiled: March 10, 2003Date of Patent: December 12, 2006Assignee: Rambus Inc.Inventors: Bruno Werner Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos, Richard M. Barth, Paul G. Davis, Ely K. Tsern
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Publication number: 20040168036Abstract: A method and apparatus for adjusting the performance of a memory system is provided. A memory control device comprises a master device including a frequency detector, a memory channel, and a memory device coupled to the master device via the memory channel. The memory device includes a decoder designed to receive a control signal from the master device. A clock recovery and alignment circuit receives the control signal from the decoder and adjusts the operating frequency of the memory device in response to the control signal.Type: ApplicationFiled: March 10, 2003Publication date: August 26, 2004Inventors: Bruno Werner Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos, Richard M. Barth, Paul G. Davis, Ely K. Tsern
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Patent number: 6553452Abstract: A synchronous dynamic random access memory device having an array of dynamic memory cells. The memory device includes input receiver circuitry to sample a value that is representative of a range of temperatures. In addition, the memory device includes a programmable register, coupled to the input receiver circuitry, to store the value that is representative of the range of temperatures.Type: GrantFiled: January 18, 2002Date of Patent: April 22, 2003Assignee: Rambus Inc.Inventors: Bruno Werner Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos, Richard M. Barth, Paul G. Davis, Ely K. Tsern
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Patent number: 6513103Abstract: A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.Type: GrantFiled: October 10, 1997Date of Patent: January 28, 2003Assignee: Rambus Inc.Inventors: Bruno Werner Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos, Richard M. Barth, Paul G. Davis, Ely K. Tsern
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Patent number: 6448813Abstract: An output driver circuit for driving a signal onto a signal line. The output driver circuit comprises at least one driver circuit and a passive network. The passive network is configured to limit the variation in the output impedance of the output driver circuit. The output driver circuit thus provides an output impedance that closely matches the loaded impedance of the signal line at all times so as to minimize secondary reflections on the signal line.Type: GrantFiled: March 6, 2001Date of Patent: September 10, 2002Assignee: Rambus Inc.Inventors: Bruno Werner Garlepp, Kevin S. Donnelly, Jared LeVan Zerbe
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Publication number: 20020087820Abstract: A method and apparatus for adjusting the performance of a memory system is provided. A memory control device comprises a master device including a frequency detector, a memory channel, and a memory device coupled to the master device via the memory channel. The memory device includes a decoder designed to receive a control signal from the master device. A clock recovery and alignment circuit receives the control signal from the decoder and adjusts the operating frequency of the memory device in response to the control signal.Type: ApplicationFiled: January 18, 2002Publication date: July 4, 2002Inventors: Bruno Werner Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos, Richard M. Barth, Paul G. Davis, Ely K. Tsern
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Publication number: 20010035768Abstract: An output driver circuit for driving a signal onto a signal line. The output driver circuit comprises at least one driver circuit and a passive network. The passive network is configured to limit the variation in the output impedance of the output driver circuit. The output driver circuit thus provides an output impedance that closely matches the loaded impedance of the signal line at all times so as to minimize secondary reflections on the signal line.Type: ApplicationFiled: March 6, 2001Publication date: November 1, 2001Applicant: Rambus Inc.Inventors: Bruno Werner Garlepp, Kevin S. Donnelly, Jared LeVan Zerbe
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Patent number: 6198307Abstract: An output driver circuit for driving a signal onto a signal line. The output driver circuit comprises at least one driver circuit and a passive network. The passive network is configured to limit the variation in the output impedance of the output driver circuit. The output driver circuit thus provides an output impedance that closely matches the loaded impedance of the signal line at all times so as to minimize secondary reflections on the signal line.Type: GrantFiled: October 26, 1998Date of Patent: March 6, 2001Assignee: Rambus Inc.Inventors: Bruno Werner Garlepp, Kevin S. Donnelly, Jared LeVan Zerbe
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Patent number: 6133773Abstract: A method and apparatus for an adjustable phase interpolator is provided. The adjustable phase interpolator includes a phase interpolator circuit that has a voltage input and a voltage output. The adjustable phase interpolator further includes a controllable capacitive load coupled to either the input or the output of the phase interpolator circuit. The controllable capacitive load is designed to add or subtract capacitance to the adjustable phase interpolator.Type: GrantFiled: October 10, 1997Date of Patent: October 17, 2000Assignee: Rambus IncInventors: Bruno Werner Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos, Leung Yu, Benedict Chung-Kwong Lau, Roxanne Vu