Abstract: A system and method to mitigate or complicate the use of differential power analysis (DPA) and simple power analysis (SPA) in the attack of a targeted integrated circuit, or device containing an integrated circuit, that is processing sensitive information. The system and method modifies the regularity of a clock that initiates the power events within the circuit such that subsequent processing of information does not always occur at the same time.

Abstract: Architecture for embedding a cryptographic engine in a processor is disclosed. An ASIC processor is embedded with a programmable processing core, such as an FPGA, with the key register and I/O registers remaining in fixed logic.

Abstract: Methods and systems are provided for a programmable parallel computation and data manipulation accelerator that may be used, for example, in cryptographic calculations. They allow acceleration of a broad variety of cryptographic algorithms and/or portions of algorithms, and are not algorithm specific. This system comprises a butterfly and inverse butterfly multiplexing permuter network and a lookup table. This system may allow replication of input registers, “expansion,” so that an individual bit may be used in multiple calculations in parallel, accelerating completion of the cryptographic algorithm. The system may allow “diffusion” of the expanded bits through the system's butterfly and inverse butterfly network, and may provide for “confusion” of the resulting bits through the system's lookup table. In some implementations, the system may allow completion of a computation within an algorithm within one clock cycle.

Abstract: Methods and systems are provided for a programmable parallel computation and data manipulation accelerator that may be used, for example, in cryptographic calculations. They allow acceleration of a broad variety of cryptographic algorithms and/or portions of algorithms, and are not algorithm specific. This system comprises a butterfly and inverse butterfly multiplexing permuter network and a lookup table. This system may allow replication of input registers, “expansion,” so that an individual bit may be used in multiple calculations in parallel, accelerating completion of the cryptographic algorithm. The system may allow “diffusion” of the expanded bits through the system's butterfly and inverse butterfly network, and may provide for “confusion” of the resulting bits through the system's lookup table. In some implementations, the system may allow completion of a computation within an algorithm within one clock cycle.

Abstract: Memory-based permutation methods and systems are provided for the permutation of data. The memory-based permutation methods and systems provide flexibility and reconfigurability while reducing size and increasing speed. They provide the ability to program a memory, such as a Random Access Memory (RAM), to implement a permutation of source data. The RAM may be reprogrammed to change the permutation pattern thereby providing the flexibility to implement any pattern of permutation from source data to output data and the reconfigurability to change that implementation as desired. Also, the size of the RAM is greatly reduced, and as the input and output data width and number of input and output data bits increase, the size and complexity of the RAM does not increase greatly or exponentially, as with typical conventional systems.

Abstract: Architecture for embedding a cryptographic engine in a processor is disclosed. An ASIC processor is embedded with a programmable processing core, such as an FPGA, with the key register and I/O registers remaining in fixed logic.

Abstract: A tamper monitor circuit detects voltage, temperature, and/or clock variations that may be associated with a circuit tampering technique, and triggers an appropriate tamper response. The tamper monitor circuit includes a reference oscillator, a detection oscillator, and a comparison circuit. The reference oscillator supplies a reference signal having a reference frequency. The detection oscillator operates at a circuit temperature and is energized with a supply voltage, and supplies a detection signal having a frequency that varies with variations in the circuit temperature, variations in the supply voltage, or both. The comparison circuit receives the reference signal and the detection signal and, in response to the reference signal, selectively determines the frequency of the detection signal, determines a frequency difference between two or more of the determined frequencies, and supplies a tamper detect signal if the determined frequency difference exceeds a predetermined difference threshold.