Abstract: Processing apparatus in the form of a parallel processing configuration having a plurality of processors and at least one shared memory that is shared between the processors. Each processor is operated at a clock speed that is lower than the clock speed of the memory.

Abstract: A circuit is for sampling an analog input signal that receives and samples an analog input signal. Sampling circuitry is clocked at a sampling frequency and samples the analog input signal at a rate corresponding to the sampling frequency. The sampling circuitry includes at least one pulse density modulator that includes a comparator configured to be clocked at the sampling frequency, to provide bandpass sampling of the analog input signal at the sampling frequency, and to produce a corresponding pulsed output that is pulse density modulated based on the analog input signal.

Abstract: A modulator circuit includes a plurality of signal processing branches, each branch having a modulator for performing a delta-sigma modulation of a respective data stream portion in order to generate a modulated signal. The modulator circuit receives an input data stream having a carrier frequency; splits the input data stream into a plurality of data stream portions. Delta-sigma modulation is performed in each branch on a respective data stream portion. The respective modulated signals from each branch are combined to form an output signal for outputting at the carrier frequency.

Abstract: A modulator circuit includes a plurality of signal processing branches, each branch having a modulator for performing a delta-sigma modulation of a respective data stream portion in order to generate a modulated signal. The modulator circuit receives an input data stream having a carrier frequency; splits the input data stream into a plurality of data stream portions. Delta-sigma modulation is performed in each branch on a respective data stream portion. The respective modulated signals from each branch are combined to form an output signal for outputting at the carrier frequency.

Abstract: Processing apparatus in the form of a parallel processing configuration having a plurality of processors and at least one shared memory that is shared between the processors. Each processor is operated at a clock speed that is lower than the clock speed of the memory.

Abstract: A circuit is for sampling an analog input signal that receives and samples an analog input signal. Sampling circuitry is clocked at a sampling frequency and samples the analog input signal at a rate corresponding to the sampling frequency. The sampling circuitry includes at least one pulse density modulator that includes a comparator configured to be clocked at the sampling frequency, to provide bandpass sampling of the analog input signal at the sampling frequency, and to produce a corresponding pulsed output that is pulse density modulated based on the analog input signal.

Abstract: A receiver (10) for receiving a wireless communication signal, such as a UWB signal, is operable in a first mode when the receiver is actively receiving a transmitted signal, and a second mode when the receiver is waiting to receive a transmitted signal. The receiver comprises an analogue-to-digital converter (20) for converting a received analogue signal into a digital signal. A receiver controller is adapted to control the operating resolution of the analogue to digital converter such that, in the first mode, the analogue-to-digital converter (20) operates at a first resolution, and, in the second mode, the analogue-to-digital converter (20) operates at a second resolution. The second resolution is lower than the first resolution, and preferably the second resolution is a 1-bit resolution.