Patents by Inventor Bryan Peng
Bryan Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240141541Abstract: An apparatus for electroplating a metal on a semiconductor substrate with high control over plated thickness on a die-level includes an ionically resistive ionically permeable element (e.g., a plate with channels), where the element allows for flow of ionic current through the element towards the substrate during electroplating, where the element includes a plurality of regions, each region having a pattern of varied local resistance, and where the pattern of varied local resistance repeats in at least two regions. An electroplating method includes providing a semiconductor substrate to an electroplating apparatus having an ionically resistive ionically permeable element or a grid-like shield having a pattern correlating with a pattern of features on the substrate, and plating metal, while the pattern on the substrate remains spatially aligned with the pattern of the element or the grid-like shield for at least a portion of the total electroplating time.Type: ApplicationFiled: March 15, 2022Publication date: May 2, 2024Inventors: Lee Peng Chua, Gabriel Hay Graham, Bryan L. Buckalew, Stephen J. Banik, II, Santosh Kumar, James Isaac Fortner, Robert Rash, Steven T. Mayer
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Publication number: 20240076795Abstract: An ionically resistive ionically permeable element for use in an electroplating apparatus includes ribs to tailor hydrodynamic environment proximate a substrate during electroplating. In one implementation, the ionically resistive ionically permeable element includes a channeled portion that is at least coextensive with a plating face of the substrate, and a plurality of ribs extending from the substrate-facing surface of the channeled portion towards the substrate. Ribs include a first plurality of ribs of full maximum height and a second plurality of ribs of smaller maximum height than the full maximum height. In one implementation the ribs of smaller maximum height are disposed such that the maximum height of the ribs gradually increases in a direction from one edge of the element to the center of the element.Type: ApplicationFiled: January 19, 2022Publication date: March 7, 2024Inventors: Stephen J. Banik, II, Gabriel Hay Graham, Bryan L. Buckalew, Robert Rash, Lee Peng Chua, Frederick Dean Wilmot, Chien-Chieh Lin
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Publication number: 20230099157Abstract: Systems, methods, and devices for fluid conduit inspection using absolute velocity of a sensor device are provided. The method includes: receiving sensor data collected by a sensor device during a measurement run from an interior of the fluid conduit while traveling along a length of the fluid conduit, the sensor device including a first magnetometer and a second magnetometer each having a fixed position in the sensor device, the fixed positions defining a separation distance between the first magnetometer and second magnetometer, the sensor data including magnetic flux data comprising first magnetic flux data collected by the first magnetometer and second magnetic flux data collected by the second magnetometer; determining a time delay between when a magnetic signal is present in the first magnetic flux data and when the magnetic signal is present in the second magnetic flux data; determining an absolute velocity of the sensor device.Type: ApplicationFiled: April 29, 2022Publication date: March 30, 2023Inventors: Anouk van Pol, Bryan Peng, Johannes Hubertus Gerardus Van Pol
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Patent number: 8148806Abstract: The package includes a substrate, a first chip, a second chip, multiple first bumps and multiple second bumps. The substrate has a first region and a second region. The first region is substantially coplanar with the second region. The first bumps connect the first chip and the second chip. The second bumps connect the first chip and the second region of the substrate, wherein the second chip is over the first region of the substrate. The second bumps have a height greater than that of the first bumps plus the second chip. The substrate does not have an opening accommodating the second chip. The first bumps may be gold bumps or solder bumps. The second bumps may be solder bumps.Type: GrantFiled: November 12, 2008Date of Patent: April 3, 2012Assignee: Megica CorporationInventors: Mou-Shiung Lin, Bryan Peng
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Publication number: 20090056988Abstract: The package includes a substrate, a first chip, a second chip, multiple first bumps and multiple second bumps. The substrate has a first region and a second region. The first region is substantially coplanar with the second region. The first bumps connect the first chip and the second chip. The second bumps connect the first chip and the second region of the substrate, wherein the second chip is over the first region of the substrate. The second bumps have a height greater than that of the first bumps plus the second chip. The substrate does not have an opening accommodating the second chip. The first bumps may be gold bumps or solder bumps. The second bumps may be solder bumps.Type: ApplicationFiled: November 12, 2008Publication date: March 5, 2009Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Bryan Peng
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Publication number: 20090057919Abstract: The package includes a substrate, a first chip, a second chip, multiple first bumps and multiple second bumps. The substrate has a first region and a second region. The first region is substantially coplanar with the second region. The first bumps connect the first chip and the second chip. The second bumps connect the first chip and the second region of the substrate, wherein the second chip is over the first region of the substrate. The second bumps have a height greater than that of the first bumps plus the second chip. The substrate does not have an opening accommodating the second chip. The first bumps may be gold bumps or solder bumps. The second bumps may be solder bumps.Type: ApplicationFiled: November 12, 2008Publication date: March 5, 2009Applicant: MEGICA CORPORATIONInventors: Mou-Shiung Lin, Bryan Peng
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Patent number: 7468551Abstract: A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.Type: GrantFiled: May 13, 2003Date of Patent: December 23, 2008Assignee: Megica CorporationInventors: Mou-Shiung Lin, Bryan Peng
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Patent number: 7247932Abstract: A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.Type: GrantFiled: May 19, 2000Date of Patent: July 24, 2007Assignee: Megica CorporationInventors: Mou-Shiung Lin, Bryan Peng
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Patent number: 7205646Abstract: The package includes a substrate, a first chip, a second chip, multiple first bumps and multiple second bumps. The substrate has a first region and a second region. The first region is substantially coplanar with the second region. The first bumps connect the first chip and the second chip. The second bumps connect the first chip and the second region of the substrate, wherein the second chip is over the first region of the substrate. The second bumps have a height greater than that of the first bumps plus the second chip. The substrate does not have an opening accommodating the second chip. The first bumps may be gold bumps or solder bumps. The second bumps may be solder bumps.Type: GrantFiled: April 22, 2003Date of Patent: April 17, 2007Assignee: Megica CorporationInventors: Mou-Shiung Lin, Bryan Peng
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Patent number: 7045901Abstract: A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.Type: GrantFiled: February 21, 2003Date of Patent: May 16, 2006Assignee: Megic CorporationInventors: Mou-Shiung Lin, Bryan Peng
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Patent number: 6791192Abstract: A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.Type: GrantFiled: February 21, 2003Date of Patent: September 14, 2004Assignee: Megic CorporationInventors: Mou-Shiung Lin, Bryan Peng
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Patent number: 6768208Abstract: A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.Type: GrantFiled: May 13, 2003Date of Patent: July 27, 2004Assignee: Megic CorporationInventors: Mou-Shiung Lin, Bryan Peng
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Publication number: 20030205826Abstract: A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.Type: ApplicationFiled: April 22, 2003Publication date: November 6, 2003Applicant: MEGIC CORPORATIONInventors: Mou-Shiung Lin, Bryan Peng
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Publication number: 20030201545Abstract: A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.Type: ApplicationFiled: May 13, 2003Publication date: October 30, 2003Applicant: MEGIC CORPORATIONInventors: Mou-Shiung Lin, Bryan Peng
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Publication number: 20030197287Abstract: A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.Type: ApplicationFiled: May 13, 2003Publication date: October 23, 2003Applicant: MEGIC CORPORATIONInventors: Mou-Shiung Lin, Bryan Peng
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Publication number: 20030127749Abstract: A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.Type: ApplicationFiled: February 21, 2003Publication date: July 10, 2003Applicant: MEGIC CorporationInventors: Mou-Shiung Lin, Bryan Peng
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Publication number: 20030122240Abstract: A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.Type: ApplicationFiled: February 21, 2003Publication date: July 3, 2003Applicant: MEGIC CorporationInventors: Mou-Shiung Lin, Bryan Peng