Abstract: Methods and apparatus for controlling a switch transition in an inductive switching circuit are disclosed. A switch driver is configured to receive an indication of current through a diode associated with a first switch and dynamically control a switch transition of a second switch based on the indication of current, so as to reduce the switch transition time, when possible, whilst maintaining a voltage transient due to the switch transition within an acceptable range.

Abstract: A power converter system for converting an input voltage at an input into an output voltage at an output may comprise a switch network comprising a reactive circuit element and a plurality of switches, switch control circuitry configured to operate the plurality of switch in a plurality of periodic, sequential states to regulate the output voltage, and reference current generating circuitry. The reference current generating circuitry may include a comparator coupled to a sensed switch of the plurality of switches and configured to compare a current flowing through the sensed switch to a reference current and current-steering circuitry coupled to the comparator configured to generate the reference current and alternate the reference current between a first reference current and a second reference current whenever the switch control circuitry changes from one state of the plurality of periodic, sequential states to another state of the plurality of periodic, sequential states.

Abstract: A switching converter with reduced dead-time and without reverse-recovery is disclosed. The switching converter includes a first power switch coupled to a second power switch, a mode detector and a controller. The mode detector is adapted to detect a mode of operation of the first power switch and the second power switch, and to identify a first period during which the first power switch is turned on and operates in a linear mode while the second power switch is turned off. The controller is adapted to bias the second power switch with a predetermined voltage during the first period to turn on the second power switch during a second period. In the second period the first power switch is operating in a saturation mode.

Abstract: Driver circuits with S-shaped gate drive voltage curves for ramp-up and ramp-down of power field effect transistors are presented. In ramp-up, the S-shaped curve rapidly ramps the gate voltage of the power FET to its threshold. This ramp-up is self-terminating. The gate voltage of the power FET is slewed through saturation with a time constant. After a predetermined time, the gate of the power FET is driven to approach the supply voltage level. In ramp-down, the S-shaped curve rapidly ramps the gate voltage of the power FET down to its threshold voltage. This ramp-down is self-terminating. The gate voltage of the power FET is slewed through saturation. The gate-source voltage of the power FET is rapidly ramped down to zero. Such S-shaped curves for the gate drive signal allow the control of the transition times of the gate drive signal to acceptable levels of voltage/current spikes and electromagnetic interference.

Abstract: A multi-level buck converter is provided with multiple control loops to regulate the output voltage across a wide duty cycle range while also regulating the flying capacitor voltage. The regulated flying capacitor voltage is exploited to drive the switch transistors that float with respect to ground.

Abstract: In an integrated circuit, a state of a switch coupled to the integrated circuit is determined by comparing a switch voltage at a first terminal of the switch to a reference voltage at a first time. If the switch voltage is higher than the reference voltage, the switch is determined to be in a first state. If the switch voltage is lower than the reference voltage, the switch voltage is stored in a storage element to produce a stored voltage. The stored voltage is compared to the switch voltage at a second time after the first time. A determination is made that the switch is in the first state if the switch voltage is higher than the stored voltage at the second time. A determination is made that the switch is in a second state if the switch voltage is not higher than the stored voltage at the second time.

Abstract: In an integrated circuit, a state of a switch coupled to the integrated circuit is determined by comparing a switch voltage at a first terminal of the switch to a reference voltage at a first time. If the switch voltage is higher than the reference voltage, the switch is determined to be in a first state. If the switch voltage is lower than the reference voltage, the switch voltage is stored in a storage element to produce a stored voltage. The stored voltage is compared to the switch voltage at a second time after the first time. A determination is made that the switch is in the first state if the switch voltage is higher than the stored voltage at the second time. A determination is made that the switch is in a second state if the switch voltage is not higher than the stored voltage at the second time.

Abstract: A voltage regulator includes first and second MOS transistors and a bipolar transistor. The first MOS transistor has a first conductivity type and has a drain coupled to a first power supply voltage terminal, a gate for receiving a first bias voltage, and a source. The second MOS transistor has a second conductivity type and has a source coupled to the first power supply voltage terminal, a drain coupled to the source of the first MOS transistor, and a gate for receiving a second bias voltage. The bipolar transistor has a collector coupled to the source of the first MOS transistor, a base for receiving a third bias voltage, and an emitter for providing an output voltage. The first MOS transistor and the second MOS transistor control a voltage level at the collector of the bipolar transistor in response to a varying power supply voltage provided to the first power supply voltage terminal.

Abstract: According to one embodiment, an integrated fault detector circuit is used to detect one or more of the open circuit and short circuit of a load connected to an integrated circuit power MOSFET driver by directly detecting the level of current flowing in a floating current source.

Abstract: According to one embodiment, an integrated fault detector circuit is used to detect one or more of the open circuit and short circuit of a load connected to an integrated circuit power MOSFET driver by directly detecting the level of current flowing in a floating current source.