Patents by Inventor Bryan R. White
Bryan R. White has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220405876Abstract: An apparatus to facilitate partitioning of a graphics device is disclosed. The apparatus includes a plurality of engines and logic to partition the plurality of engines to facilitate independent access to each engine within the plurality of engines.Type: ApplicationFiled: May 6, 2022Publication date: December 22, 2022Applicant: Intel CorporationInventors: Abhishek R. Appu, Balaji Vembu, Altug Koker, Bryan R. White, David J. Cowperthwaite, Joydeep Ray, Murali Ramadoss
-
Patent number: 11514550Abstract: An apparatus and method for managing pipes and planes within a virtual graphics processing engine. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising one or more display pipes to render one or more display planes, each of the one or more display pipes comprising a set of graphics processing hardware resources for executing graphics commands and rendering graphics images in the one or more display planes; and pipe and plane management hardware logic to manage pipe and plane assignment, the pipe and plane management hardware logic to associate a first virtual machine (VM) with one or more virtual display planes and to maintain a mapping between the one or more virtual display planes and at least one physical display plane.Type: GrantFiled: June 30, 2020Date of Patent: November 29, 2022Assignee: INTEL CORPORATIONInventors: Yunbiao Lin, Changliang Wang, Satyanantha Ramagopal Musunuri, David Puffer, David J. Cowperthwaite, Bryan R. White, Balaji Vembu
-
Patent number: 11341600Abstract: An apparatus to facilitate partitioning of a graphics device is disclosed. The apparatus includes a plurality of engines and logic to partition the plurality of engines to facilitate independent access to each engine within the plurality of engines.Type: GrantFiled: November 13, 2019Date of Patent: May 24, 2022Assignee: Intel CorporationInventors: Abhishek R. Appu, Balaji Vembu, Altug Koker, Bryan R. White, David J. Cowperthwaite, Joydeep Ray, Murali Ramadoss
-
Publication number: 20220004635Abstract: An apparatus is disclosed. The apparatus comprises a trusted device including a first integrated circuit (IC) die comprising a first plurality of hardware devices and a second IC die comprising a second plurality of hardware devices and cryptographic processor to operate as a root of trust to manage an input/output (I/O) functional state of each of the hardware devices.Type: ApplicationFiled: September 21, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Daniel Nemiroff, Vidhya Krishnan, Bryan R. White
-
Patent number: 11157431Abstract: In one embodiment, a method includes: receiving, in a root tile of an accelerator device having a plurality of tiles, a message from a processor, the message comprising a register write request to a register of a first remote tile of the plurality of remote tiles; decoding, in an endpoint controller of the root tile, a system address of the message to identify a destination tile for the message, based at least in part on a base address register decode of the system address; and in response to identifying the first remote tile as the destination tile, updating a first portion of an address offset field of the system address to a predetermined value and directing the message to the first remote tile coupled to the root tile via a sideband interconnect. Other embodiments are described and claimed.Type: GrantFiled: June 20, 2019Date of Patent: October 26, 2021Assignee: Intel CorporationInventors: Bryan R. White, Aravindh Anantaraman, Ankur Shah, Altug Koker, David Puffer, Aditya Navale
-
Patent number: 10908939Abstract: An apparatus and method are described for fine grained sharing of graphics processing resources for example, one embodiment of a graphics processing apparatus comprises: a plurality of command buffers to store work elements from a plurality of virtual machines or applications, each work element indicating a command to be processed by graphics hardware and data identifying the virtual machine or application which generated the work element; a plurality of doorbell registers or memory regions, each doorbell register or memory region associated with a particular virtual machine or application, a virtual machine or application to store an indication in its doorbell register or memory region when it has stored a work element to a command buffer; and a work scheduler to read a work element from a command buffer responsive to detecting an indication in a doorbell register, the work scheduler to combine work elements from multiple virtual machines or applications in a submission to a graphics engine, the graphics engType: GrantFiled: January 31, 2017Date of Patent: February 2, 2021Assignee: Intel CorporationInventors: Balaji Vembu, Altug Koker, David Puffer, Murali Ramadoss, Bryan R. White, Hema C. Nalluri, Aditya Navale
-
Publication number: 20200394749Abstract: An apparatus and method for managing pipes and planes within a virtual graphics processing engine. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising one or more display pipes to render one or more display planes, each of the one or more display pipes comprising a set of graphics processing hardware resources for executing graphics commands and rendering graphics images in the one or more display planes; and pipe and plane management hardware logic to manage pipe and plane assignment, the pipe and plane management hardware logic to associate a first virtual machine (VM) with one or more virtual display planes and to maintain a mapping between the one or more virtual display planes and at least one physical display plane.Type: ApplicationFiled: June 30, 2020Publication date: December 17, 2020Inventors: Yunbiao LIN, Changliang WANG, Satyanantha Ramagopal MUSUNURI, David PUFFER, David J. COWPERTHWAITE, Bryan R. WHITE, Balaji VEMBU
-
Patent number: 10831483Abstract: An apparatus to facilitate doorbell notifications is disclosed. The apparatus includes memory-mapped I/O (MMIO) base address registers including a physical function (PF) and plurality of virtual functions (VF), wherein each function's base address register comprises a plurality of doorbell pages and doorbell hardware including doorbell registers, each having an assignable function identifier (ID) and offset, and comprising a plurality of doorbells to activate a doorbell notification in response to receiving a doorbell trigger from an associated doorbell page set upon detection of an access request.Type: GrantFiled: April 29, 2019Date of Patent: November 10, 2020Assignee: Intel CorporationInventors: Bryan R. White, Ankur N. Shah, Altug Koker, David Puffer, Aditya Navale
-
Publication number: 20200341766Abstract: An apparatus to facilitate doorbell notifications is disclosed. The apparatus includes memory-mapped I/O (MMIO) base address registers including a physical function (PF) and plurality of virtual functions (VF), wherein each function's base address register comprises a plurality of doorbell pages and doorbell hardware including doorbell registers, each having an assignable function identifier (ID) and offset, and comprising a plurality of doorbells to activate a doorbell notification in response to receiving a doorbell trigger from an associated doorbell page set upon detection of an access request.Type: ApplicationFiled: April 29, 2019Publication date: October 29, 2020Applicant: Intel CorporationInventors: Bryan R. White, Ankur N. Shah, Altug Koker, David Puffer, Aditya Navale
-
Patent number: 10706493Abstract: An apparatus and method for managing pipes and planes within a virtual graphics processing engine. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising one or more display pipes to render one or more display planes, each of the one or more display pipes comprising a set of graphics processing hardware resources for executing graphics commands and rendering graphics images in the one or more display planes; and pipe and plane management hardware logic to manage pipe and plane assignment, the pipe and plane management hardware logic to associate a first virtual machine (VM) with one or more virtual display planes and to maintain a mapping between the one or more virtual display planes and at least one physical display plane.Type: GrantFiled: December 29, 2017Date of Patent: July 7, 2020Assignee: Intel CorporationInventors: Yunbiao Lin, Changliang Wang, Satyanantha Ramagopal Musunuri, David Puffer, David J. Cowperthwaite, Bryan R White, Balaji Vembu
-
Publication number: 20200193555Abstract: An apparatus to facilitate partitioning of a graphics device is disclosed. The apparatus includes a plurality of engines and logic to partition the plurality of engines to facilitate independent access to each engine within the plurality of engines.Type: ApplicationFiled: November 13, 2019Publication date: June 18, 2020Applicant: Intel CorporationInventors: Abhishek R. Appu, Balaji Vembu, Altug Koker, Bryan R. White, David J. Cowperthwaite, Joydeep Ray, Murali Ramadoss
-
Patent number: 10678623Abstract: Various systems and methods for error handling are described herein. A system for error reporting and handling includes a common error handler that handles errors for a plurality of hardware devices, where the common error handler is operable with other parallel error reporting and handling mechanisms. The common error handler may be used to receive an error message from a hardware device, the error message related to an error; identify a source of the error message; identify a class of the error; identify an error definition of the error; determine whether the error requires a diagnostics operation as part of the error handling; initiate the diagnostics operation when the error requires the diagnostics operation; and clear the error at the hardware device.Type: GrantFiled: November 20, 2017Date of Patent: June 9, 2020Assignee: Intel CorporationInventors: Michael N. Derr, Balaji Vembu, Michael Mishaeli, Brent Chartrand, Bryan R White, Gustavo Espinosa, Prashant D. Chaudhari
-
Patent number: 10482562Abstract: An apparatus to facilitate partitioning of a graphics device is disclosed. The apparatus includes a plurality of engines and logic to partition the plurality of engines to facilitate independent access to each engine within the plurality of engines.Type: GrantFiled: April 21, 2017Date of Patent: November 19, 2019Assignee: INTEL CORPORATIONInventors: Abhishek R. Appu, Balaji Vembu, Altug Koker, Bryan R. White, David J. Cowperthwaite, Joydeep Ray, Murali Ramadoss
-
Publication number: 20190303334Abstract: In one embodiment, a method includes: receiving, in a root tile of an accelerator device having a plurality of tiles, a message from a processor, the message comprising a register write request to a register of a first remote tile of the plurality of remote tiles; decoding, in an endpoint controller of the root tile, a system address of the message to identify a destination tile for the message, based at least in part on a base address register decode of the system address; and in response to identifying the first remote tile as the destination tile, updating a first portion of an address offset field of the system address to a predetermined value and directing the message to the first remote tile coupled to the root tile via a sideband interconnect. Other embodiments are described and claimed.Type: ApplicationFiled: June 20, 2019Publication date: October 3, 2019Inventors: Bryan R. White, Aravindh Anantaraman, Ankur Shah, Altug Koker, David Puffer, Aditya Navale
-
Publication number: 20190206017Abstract: An apparatus and method for managing pipes and planes within a virtual graphics processing engine. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising one or more display pipes to render one or more display planes, each of the one or more display pipes comprising a set of graphics processing hardware resources for executing graphics commands and rendering graphics images in the one or more display planes; and pipe and plane management hardware logic to manage pipe and plane assignment, the pipe and plane management hardware logic to associate a first virtual machine (VM) with one or more virtual display planes and to maintain a mapping between the one or more virtual display planes and at least one physical display plane.Type: ApplicationFiled: December 29, 2017Publication date: July 4, 2019Inventors: YUNBIAO LIN, CHARLIE L. WANG, SATYANANTHA RAMAGOPAL MUSUNURI, DAVID PUFFER, DAVID J. COWPERTHWAITE, BRYAN R. WHITE, BALAJI VEMBU
-
Publication number: 20190050279Abstract: Various systems and methods for error handling are described herein. A system for error reporting and handling includes a common error handler that handles errors for a plurality of hardware devices, where the common error handler is operable with other parallel error reporting and handling mechanisms. The common error handler may be used to receive an error message from a hardware device, the error message related to an error; identify a source of the error message; identify a class of the error; identify an error definition of the error; determine whether the error requires a diagnostics operation as part of the error handling; initiate the diagnostics operation when the error requires the diagnostics operation; and clear the error at the hardware device.Type: ApplicationFiled: November 20, 2017Publication date: February 14, 2019Inventors: Michael N. Derr, Balaji Vembu, Michael Mishaeli, Brent Chartrand, Bryan R. White, Gustavo Espinosa, Prashant D. Chaudhari
-
Publication number: 20180308198Abstract: An apparatus to facilitate partitioning of a graphics device is disclosed. The apparatus includes a plurality of engines and logic to partition the plurality of engines to facilitate independent access to each engine within the plurality of engines.Type: ApplicationFiled: April 21, 2017Publication date: October 25, 2018Applicant: Intel CorporationInventors: Abhishek R. Appu, Balaji Vembu, Altug Koker, Bryan R. White, David J. Cowperthwaite, Joydeep Ray, Murali Ramadoss
-
Publication number: 20180218530Abstract: An apparatus and method are described for fine grained sharing of graphics processing resources for example, one embodiment of a graphics processing apparatus comprises: a plurality of command buffers to store work elements from a plurality of virtual machines or applications, each work element indicating a command to be processed by graphics hardware and data identifying the virtual machine or application which generated the work element; a plurality of doorbell registers or memory regions, each doorbell register or memory region associated with a particular virtual machine or application, a virtual machine or application to store an indication in its doorbell register or memory region when it has stored a work element to a command buffer; and a work scheduler to read a work element from a command buffer responsive to detecting an indication in a doorbell register, the work scheduler to combine work elements from multiple virtual machines or applications in a submission to a graphics engine, the graphics engType: ApplicationFiled: January 31, 2017Publication date: August 2, 2018Inventors: BALAJI VEMBU, ALTUG KOKER, DAVID PUFFER, MURALI RAMADOSS, BRYAN R. WHITE, HEMA C. NALLURI, ADITYA NAVALE
-
Patent number: 9886934Abstract: Described herein are technologies related to a ensuring that graphics commands and graphics context are offloading and scheduled for consumption as the commands and graphics context are sent from coherent to non-coherent memory/fabric in a “processor to processor” handoff or transaction.Type: GrantFiled: December 24, 2014Date of Patent: February 6, 2018Assignee: Intel CorporationInventors: Bryan R. White, Balaji Vembu, Murali Ramadoss, Altug Koker, Aditya Navale
-
Publication number: 20160189681Abstract: Described herein are technologies related to a ensuring that graphics commands and graphics context are offloading and scheduled for consumption as the commands and graphics context are sent from coherent to non-coherent memory/fabric in a “processor to processor” handoff or transaction.Type: ApplicationFiled: December 24, 2014Publication date: June 30, 2016Inventors: Bryan R. White, Balaji Vembu, Murali Ramadoss, Altug Koker, Aditya Navale