Patents by Inventor Bryan Tracy

Bryan Tracy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9493778
    Abstract: Methods for enhancing single cross-over homologous recombination in gram positive bacteria are presented. These methods provide enhanced capability to genetically modify gram positive bacteria.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 15, 2016
    Assignee: Elcriton, Inc.
    Inventors: Bryan Tracy, Eleftherios Papoutsakis
  • Publication number: 20130203170
    Abstract: Methods for enhancing single cross-over homologous recombination in gram positive bacteria are presented. These methods provide enhanced capability to genetically modify gram positive bacteria.
    Type: Application
    Filed: March 14, 2013
    Publication date: August 8, 2013
    Inventors: Bryan Tracy, Eleftherios Papoutsakis
  • Publication number: 20110117655
    Abstract: Methods for effecting homologous recombination in a bacterium of the Clostridia family are described. These methods provide enhanced capability to genetically modify clostridia.
    Type: Application
    Filed: November 18, 2010
    Publication date: May 19, 2011
    Inventors: Bryan Tracy, Eleftherios Papoutsakis
  • Patent number: 6534869
    Abstract: A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms first, which subsequently volumetrically contracts, thereby forming a titanium aluminide compound, with the contraction being absorbed by the aluminum. Because the alloy is reacted to form the metal compound prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced.
    Type: Grant
    Filed: July 29, 1998
    Date of Patent: March 18, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bryan Tracy, Paul R. Besser, Minh Van Ngo
  • Publication number: 20010040295
    Abstract: A method for making 0.25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced.
    Type: Application
    Filed: July 29, 1998
    Publication date: November 15, 2001
    Inventors: BRYAN TRACY, PAUL R. BESSER, MINH VAN NGO
  • Patent number: 6011619
    Abstract: A semiconductor wafer optical scanning system and method for determining defects on a semiconductor wafer is disclosed. The method for determining wafer defects is based on maximum allowable defects on a swath basis, rather than maximum allowable defects on a wafer basis. The method step include determining the scanned area of an individual swath that is based on a recipe set-up, consistent with the capability of the optical scanning equipment being used and the particular semiconductor wafer being tested for defects. The predetermined swath area is supplied and stored in the optical scanning system along with the maximum allowable defect density determined by the user. By using the predetermined maximum allowable defects for a swath as a limit, defect analysis may be performed on the entire wafer. The optical scanning system would stop acquiring defects for the current swath being analyzed whenever the defect limit is reached, or until the swath defect analysis has been completed.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: January 4, 2000
    Assignee: Advanced Micro Devices
    Inventors: Paul J. Steffan, Bryan Tracy, Ming Chun Chen
  • Patent number: 5882738
    Abstract: An ion implant process is disclosed for forming an amorphous structure in a semiconductor metallization barrier layer, which barrier may be a pure metal barrier, such as titanium, tantalum, tungsten, or metal compound barrier, such as titanium nitride, or titanium-tungsten. The implant is preferably an ion of the barrier metal being used, which is implanted such that an amorphous (texture-less non-crystalline) layer is produced. Other implant species, such as nitrogen or noble gases, such as neon or argon may also be used. Subsequent deposition of the interconnect metallization (typically Al or Cu) results in an interconnect metal structure having a high degree of texture which is characterized by a very narrow distribution of crystallographic orientations in the Al or Cu film. The highly textured Al or Cu metallization results in optimizing the interconnect metal for maximum electromigration performance.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: March 16, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard C. Blish, II, Bryan Tracy
  • Patent number: 5864199
    Abstract: Electron beam emitting filaments having a tip with a radius of curvature less than about 50 .ANG. are produced using focused ion beam milling. In one embodiment, platinum is deposited on a tungsten loop electron beam filament and sharpened using focused ion beam milling to a radius of curvature less than about 50 .ANG..
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: January 26, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Roger L. Alvis, Janice Gray, Bryan Tracy
  • Patent number: 5770519
    Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a reservoir of metal having a high resistance to electromigration. The reservoir is made from a conformal layer of copper, or gold deposited over the via to form a copper, or gold plug located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the reservoir from diffusing into the insulating layer. The barrier layer and reservoir may be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and reservoir may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: June 23, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard K. Klein, Darrell Erb, Steven Avanzino, Robin Cheung, Scott Luning, Bryan Tracy, Subhash Gupta, Ming-Ren Lin
  • Patent number: 5727978
    Abstract: Electron beam emitting filaments having a tip with a radius of curvature less than about 50 .ANG. are produced using focused ion beam milling. In one embodiment, platinum is deposited on a tungsten loop electron beam filament and sharpened using focused ion beam milling to a radius of curvature less than about 50 .ANG..
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: March 17, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Roger L. Alvis, Janice Gray, Bryan Tracy
  • Patent number: 5646448
    Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.
    Type: Grant
    Filed: August 19, 1996
    Date of Patent: July 8, 1997
    Assignee: Advanced Micro Devices
    Inventors: Richard K. Klein, Darrell Erb, Steven Avanzino, Robin Cheung, Scott Luning, Bryan Tracy, Subhash Gupta, Ming-Ren Lin
  • Patent number: 5639691
    Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.
    Type: Grant
    Filed: January 24, 1996
    Date of Patent: June 17, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard K. Klein, Darrell M. Erb, Steven Avanzino, Robin Cheung, Scott Luning, Bryan Tracy, Subhash Gupta, Ming-Ren Lin