Patents by Inventor Bryant Bigbee
Bryant Bigbee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8458464Abstract: A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events.Type: GrantFiled: August 26, 2010Date of Patent: June 4, 2013Assignee: Intel CorporationInventors: Francis X. McKeen, Lawrence O. Smith, Benjamin Crawford Chaffin, Michael P. Cornaby, Bryant Bigbee
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Publication number: 20130054940Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.Type: ApplicationFiled: September 10, 2012Publication date: February 28, 2013Inventors: Hong Wang, John Shen, Ed Grochowski, James Paul Held, Bryant Bigbee, Shivnandan D. Kaushik, Gautham Chinya, Xiang Zou, Per Hammarlund, Xinmin Tian, Anil Aggarwal, Scott Dion Rodgers, Prashant Sethi, Baiju V. Patel, Richard Andrew Hankins
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Patent number: 8332619Abstract: A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.Type: GrantFiled: December 8, 2011Date of Patent: December 11, 2012Assignee: Intel CorporationInventors: Quinn A. Jacobson, Hong Wang, John P. Shen, Gautham N. Chinya, Per Hammarlund, Xiang Zou, Bryant Bigbee, Shivnandan D. Kaushik
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Publication number: 20120084536Abstract: A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.Type: ApplicationFiled: December 8, 2011Publication date: April 5, 2012Inventors: Quinn A. Jacobson, Hong Wang, John Shen, Gautham N. Chinya, Per Hammarlund, Xiang Zou, Bryant Bigbee, Shivnandan D. Kaushik
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Publication number: 20110314480Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.Type: ApplicationFiled: August 30, 2011Publication date: December 22, 2011Inventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Zou Xiang, Baiju V. Patel, Jason W. Brandt, Anil Aggarwal, John L. Reid
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Publication number: 20110271090Abstract: In one embodiment, the present invention includes a method to establish a secure pre-boot environment in a computer system; and perform at least one secure operation in the secure environment. In one embodiment, the secure operation may be storage of a secret in the secure pre-boot environment.Type: ApplicationFiled: July 1, 2011Publication date: November 3, 2011Inventors: Vincent J. Zimmer, Bryant Bigbee, Andrew J. Fish, Mark S. Doran
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Patent number: 8028295Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.Type: GrantFiled: September 30, 2005Date of Patent: September 27, 2011Assignee: Intel CorporationInventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Xiang Zou, Baiju V. Patel, Jason W. Brandt, Anil Aggarwal, John L. Reid
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Patent number: 7974416Abstract: In one embodiment, the present invention includes a method to establish a secure pre-boot environment in a computer system; and perform at least one secure operation in the secure environment. In one embodiment, the secure operation may be storage of a secret in the secure pre-boot environment.Type: GrantFiled: November 27, 2002Date of Patent: July 5, 2011Assignee: Intel CorporationInventors: Vincent J. Zimmer, Bryant Bigbee, Andrew J. Fish, Mark S. Doran
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Publication number: 20110087867Abstract: A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.Type: ApplicationFiled: December 16, 2010Publication date: April 14, 2011Inventors: Quinn A. Jacobson, Hong Wang, John Shen, Gautham N. Chinya, Per Hammarlund, Xiang Zou, Bryant Bigbee, Shivnandan D. Kaushik
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Patent number: 7882339Abstract: A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.Type: GrantFiled: June 23, 2005Date of Patent: February 1, 2011Assignee: Intel CorporationInventors: Quinn A. Jacobson, Hong Wang, John Shen, Gautham N. Chinya, Per Hammarlund, Xiang Zou, Bryant Bigbee, Shivnandan D. Kaushik
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Publication number: 20100332760Abstract: A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events.Type: ApplicationFiled: August 26, 2010Publication date: December 30, 2010Inventors: Francis X. McKeen, Lawrence O. Smith, Benjamin Crawford Chaffin, Michael P. Cornaby, Bryant Bigbee
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Publication number: 20100325445Abstract: A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events.Type: ApplicationFiled: August 26, 2010Publication date: December 23, 2010Inventors: Francis X. McKeen, Lawrence O. Smith, Benjamin Crawford Chaffin, Michael P. Cornaby, Bryant Bigbee
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Publication number: 20100325354Abstract: A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events.Type: ApplicationFiled: August 26, 2010Publication date: December 23, 2010Inventors: Francis X. McKeen, Lawrence O. Smith, Benjamin Crawford Chaffin, Michael P. Cornaby, Bryant Bigbee
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Patent number: 7849465Abstract: Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be activated, in response to the condition, with limited intervention of an operating system. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect an architecturally-defined condition. The apparatus may include an event handler to handle a yield event generated when the architecturally-defined condition has been detected. An architectural mechanism, including processor instructions and channel registers, may be utilized to allow user-level code to enable the yield event mechanism. Other embodiments are also described and claimed.Type: GrantFiled: May 19, 2005Date of Patent: December 7, 2010Assignee: Intel CorporationInventors: Xiang Zou, Hong Wang, Scott Dion Rodgers, Darrell D. Boggs, Bryant Bigbee, Shivanandan Kaushik, Anil Aggarwal, Ittai Anati, Doron Orenstein, Per Hammarlund, John Shen, Larry O. Smith, James B. Crossland, Chris J. Newburn
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Patent number: 7810083Abstract: Method, apparatus and system embodiments to provide user-level creation, control and synchronization of OS-invisible “shreds” of execution via an abstraction layer for a system that includes one or more sequencers that are sequestered from operating system control. For at least one embodiment, the abstraction layer provides sequestration logic, proxy execution logic, transition detection and shred suspension logic, and sequencer arithmetic logic. Other embodiments are also described and claimed.Type: GrantFiled: December 30, 2004Date of Patent: October 5, 2010Assignee: Intel CorporationInventors: Gautham N. Chinya, Hong Wang, Xiang Zou, James Paul Held, Prashant Sethi, Trung Diep, Anil Aggarwal, Baiju V. Patel, Shiv Kaushik, Bryant Bigbee, John Shen, Richard A. Hankins, John L. Reid
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Patent number: 7793111Abstract: A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events.Type: GrantFiled: September 28, 2000Date of Patent: September 7, 2010Assignee: Intel CorporationInventors: Francis X. McKeen, Lawrence O. Smith, Benjamin Crawford Chaffin, Michael P. Cornaby, Bryant Bigbee
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Patent number: 7743233Abstract: Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.Type: GrantFiled: April 5, 2005Date of Patent: June 22, 2010Assignee: Intel CorporationInventors: Hong Wang, Gautham N. Chinya, Richard A. Hankins, Shivnandan D. Kaushik, Bryant Bigbee, John Shen, Per Hammarlund, Xiang Zou, Jason W. Brandt, Prashant Sethi, Douglas M. Carmean, Baiju V. Patel, Scott Dion Rodgers, Ryan N. Rakvic, John L. Reid, David K. Poulsen, Sanjiv M. Shah, James Paul Held, James Charles Abel
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Publication number: 20070214342Abstract: Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture to allow a user to improve software running on a processing resources on a per-thread basis in real-time and without incurring significant processing overhead.Type: ApplicationFiled: September 23, 2005Publication date: September 13, 2007Inventors: Chris Newburn, Robert Knight, Robert Geva, Dion Rodgers, Xiang Zou, Hong Wang, Bryant Bigbee, Ittai Anati
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Publication number: 20070157211Abstract: In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.Type: ApplicationFiled: December 29, 2005Publication date: July 5, 2007Inventors: Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund, Dion Rodgers, Gautham Chinya, Baiju Patel, Shiv Kaushik, Bryant Bigbee, Gad Sheaffer, Yoav Talgam, Yuval Yosef, James Held
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Publication number: 20070079301Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread.Type: ApplicationFiled: September 30, 2005Publication date: April 5, 2007Inventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Xiang Zou, Baiju Patel, Jason Brandt, Anil Aggarwal, John Reid