Abstract: A first type memory and a second type memory may be identified in a computing system. The second type memory is slower than the first type memory while having a greater storage capacity compared to the first type memory. An application process executing in the computing system may be identified. A region of the first type memory may be provided as a cache of the second type memory for the application process.

Abstract: A computer-implemented method, in accordance with one embodiment, includes generating multiple versions of software from the same source code. Each of the versions is installed onto a corresponding, unique hardware system, the hardware systems being redundant relative to one another. When the versions are run on the respective hardware systems, the resulting respective executions of the versions are different.

Abstract: Various embodiments are provided herein for clearing memory of system in a computing environment. A zero-filled cache line with a single z-bit per entry in the cache directory may be defined. The “z” is a positive integer. A plurality of instruction set architecture (“ISA”) instructions are provided with a single z-bit in a cache line as defined in a cache directory to clear an entire cache line.

Abstract: An apparatus, a method, and a computer program product are provided that provide confidential computing on virtual machines by securing input/output operations between a virtual machine and a device. The method includes receiving an input/output (I/O) transaction from an I/O device requesting data stored memory from a virtual machine. The I/O transaction includes a virtual memory address and a bus device function. The method also includes associating the I/O transaction with a key slot associated with the virtual machine and retrieving, using the key slot, an encryption key used to encrypt and decrypt the data. The method further includes retrieving the data located at a physical memory address in physical memory relating to the virtual memory address of the data being requested and decrypting, during a read operation, the data using the encryption key for I/O transmission. The method also includes transmitting the decrypted data to the I/O device.

Abstract: Computation, placement, and accessing of error correcting codes (ECC) in a computer system data cache enabling partial reads and writes to each line of data in the cache. For storing multiple compressed blocks, received at differing time periods, in a single cache line, the ECC for the first compressed block is stored in the ECC field of the cache and the ECC for the second and subsequently received compressed blocks is appended to the compressed data. Additionally, an auxiliary ECC cache may be constructed for temporarily holding a partial ECC for a partial read/write, and a new ECC for the partial read/write is computed using the partial ECC.

Abstract: An intrusion detection and recovery system includes a copying module that creates a point-in-time copy of a storage level logical unit, the point-in-time copy including a volume copy of the storage level logical unit and signatures of the storage level logical unit, a comparison module that compares at least a portion of the point-in-time copy with a previous copy of the storage level logical unit, a judging module that, based on results of the comparison module, judges if a modification has occurred. A signature of the point-in-time copy is compared with a signature of the previous copy to detect a sign of an intrusion. The signatures of the storage level logical unit include encoded data of files of the storage level logical unit that are monitored in the point-in-time copy.

Abstract: A multi-purpose server cache directory in a computing environment is provided. One of a plurality of operation modes may be selectively enabled or disabled, by a cache directory, based on a computation phase, data type, and data pattern for caching data in a cache having a plurality of address tags in the cache directory greater than a number of data lines in a cache array.

Abstract: Various embodiments are provided herein for compressing data in latency-critical processor links of a computing system in a computing environment. One or more cache lines may be dynamically compressed at a lowest level of a networking stack based on one or more of a plurality of parameters prior to transferring a single-cache line, where the networking stack includes a framer and a data link layer.

Abstract: A central processing unit (CPU) system including a CPU core can include an adaptive cache compressor, which is capable of monitoring a miss profile of a cache. The adaptive cache compressor can compare the miss profile to a miss threshold. Based on this comparison, the adaptive cache compressor can determine whether to enable compression of the cache.

Abstract: A cache compression predictor can be coupled to a central processing unit (CPU) CPU core. The CPU core can read a cache line from a cache. Upon the CPU core reading the cache line, the cache compression predictor can predict whether the cache line is a compressed cache line or an uncompressed cache line.

Abstract: Computation, placement, and accessing of error correcting codes (ECC) in a computer system data cache enabling partial reads and writes to each line of data in the cache. For storing multiple compressed blocks, received at differing time periods, in a single cache line, the ECC for the first compressed block is stored in the ECC field of the cache and the ECC for the second and subsequently received compressed blocks is appended to the compressed data. Additionally, an auxiliary ECC cache may be constructed for temporarily holding a partial ECC for a partial read/write, and a new ECC for the partial read/write is computed using the partial ECC.

Abstract: Embodiments include performing decompression of a file. Aspects include receiving a compressed input stream for the file and processing the compressed input stream, by two or more pipelines in parallel, to create an output vector, wherein each pipeline includes a first decoder and a second decoder. Aspects also include writing, by each of the two or more pipelines, entries onto a scratchpad in an order defined by the output vector and writing one or more entries from the scratchpad to a main history buffer based on a determination that a validity field of the one or more entries has a value of true.

Abstract: Embodiments for providing enhanced location-aware protection of latches in a computing environment are provided. One or more latches are combined in one or more of a plurality of bounding boxes on a two-dimensional circuit design layout based on one or more rules. A location-aware interleaving of error correction codes (“ECC”) and burst error correction codes may be selectively applied to one or more latches in those of the plurality of bounding boxes, where multiple bit errors are corrected.

Abstract: An apparatus, a method, and a computer program product are provided that provide confidential computing on virtual machines by securing input/output operations between a virtual machine and a device. The method includes establishing an input/output (I/O) device with an encryption key associated with a virtual machine and transmitting, by the I/O device, an I/O transaction requesting encrypted data stored in physical memory by the virtual machine. the I/O transaction includes a direct memory access (DMA) memory address and a bus device function. The method also includes retrieving, by an input/output memory management unit (IOMMU), the encrypted data mapped from the DMA memory address to a physical memory address in the physical memory and transmitting, by the IOMMU, the encrypted data to the I/O device. The method further includes decrypting, by the I/O device, the encrypted data using the encryption key associated with the virtual machine and processing the decrypted data.

Abstract: An apparatus, a method, and a computer program product are provided that provide confidential computing on virtual machines by securing input/output operations between a virtual machine and a device. The method includes receiving an input/output (I/O) transaction from an I/O device requesting data stored memory from a virtual machine. The I/O transaction includes a virtual memory address and a bus device function. The method also includes associating the I/O transaction with a key slot associated with the virtual machine and retrieving, using the key slot, an encryption key used to encrypt and decrypt the data. The method further includes retrieving the data located at a physical memory address in physical memory relating to the virtual memory address of the data being requested and decrypting, during a read operation, the data using the encryption key for I/O transmission. The method also includes transmitting the decrypted data to the I/O device.

Abstract: Trustworthiness of an accelerator in heterogenous systems is increased. A workload of an application is offloaded to an accelerator for the accelerator to perform the workload. The accelerator is ensured to generate an output of the workload based on offloading the workload. The accelerator is identified as generating an output of the workload based on offloading the workload. Both an input and the output of the workload are ensured to be authentic based on offloading the workload to the accelerator. Both the input and the output of the workload are ensured to be securely transmitted based on offloading the workload to the accelerator.

Abstract: A multi-purpose server cache directory in a computing environment is provided. One of a plurality of operation modes may be selectively enabled or disabled, by a cache directory, based on a computation phase, data type, and data pattern for caching data in a cache having a plurality of address tags in the cache directory greater than a number of data lines in a cache array.

Abstract: A first type memory and a second type memory may be identified in a computing system. The second type memory is slower than the first type memory while having a greater storage capacity compared to the first type memory. An application process executing in the computing system may be identified. A region of the first type memory may be provided as a cache of the second type memory for the application process.

Abstract: Data may be transferred from a volatile memory to a non-volatile memory using a persistent power enabled on-chip data processor upon detecting a power loss from a primary power source. The one or more emergency power supplies are attached to the volatile memory, the non-volatile memory, and the persistent power enabled on-chip data processor to assist with the transferring of data.

Abstract: Low latency in a non-uniform cache access (“NUCA”) cache in a computing environment is provided. A first compressed cache line is interleaved with a second compressed cache line into a single cache line of the NUCA cache, where data of the first compressed cache line is stored in one or more even sectors in the single cache line and stored in zero or more odd sectors in the single cache line after the data fills the one or more even sectors, and data of the second compressed cache line is stored in the one or more odd sectors in the single cache line and stored in zero or more even sectors in the single cache line after the data fills the one or more odd sectors.