Abstract: A method, system and computer program product are provided for implementing attachment of a user mode foreign device to a memory channel in a computer system. A user mode foreign device is attached to the memory channel using memory mapping of device registers and device buffers to the processor address space. The storage capacity on the device is doubly mapped in the address space creating separate control and data address spaces to allow user mode processes to control the device therefore eliminating the need for software system calls. A processor Memory Management Unit (MMU) coordinates multiple user processes accessing the device registers and buffers providing address space protection of each of interfaces, shifting device protection to the processor MMU from system software.

Abstract: Embodiments of the invention provide a method, system and computer program product for re-locating virtual machines (VM) in a data center environment. In an embodiment of the invention, a method for intelligent VM relocation includes selecting a set of VMs for relocation over a data communications network within a data center from one or more source physical machines to one or more target physical machines. The method also includes computing in memory of a computer in the data center a VM mobility cost for relocating the set of the VMs. The method yet further includes determining whether or not the VM mobility cost exceeds available resources in the data communications network. Finally, the method includes relocating the set of the VMs only it is determined that the VM mobility cost does not exceed the available resources of the data communications network.

Abstract: Consistency of data stored in persistent memory is maintained using separate commit and harden operations for a transaction. A transaction is committed with a processing device, the committing including marking an end of an atomic operation on a modified object from the transaction, creating a new copy of the modified object, and storing a mapping of the modified object to the new copy of the modified object in a recorded log. A checksum identifying the modified object is created and stored in the recorded log. The transaction is hardened by storing the modified object and the recorded log from cache into persistent memory.

Abstract: A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. When two translation table entries reference identical fragments in a memory block, one of the translation table entries is changed to refer to the same memory block referenced in the other translation table entry, which frees up a memory block. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries. When a translation table has a private delta, its delta bit is set.

Abstract: A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. When two translation table entries reference identical fragments in a memory block, one of the translation table entries is changed to refer to the same memory block referenced in the other translation table entry, which frees up a memory block. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries. When a translation table has a private delta, its delta bit is set.

Abstract: Embodiments relate to personalized low latency communications. A method may include receiving a description of content of a message, receiving recipient data corresponding to at least two possible recipients within a population of possible recipients, and selecting a relevant subpopulation of the population. The selecting may include, for each of the at least two possible recipients, ranking a strength of an indirect relationship between the description and the recipient data. The indirect relationship may be based on the description, the recipient data and at least one additional data source. The selecting may also include, for each of the at least two possible recipients, adding a possible recipient to the relevant subpopulation based on the ranking of the indirect relationship associated with the possible recipient. The method may further include initiating a two-way communication channel between a sender of the message and the relevant subpopulation.

Abstract: Embodiments relate to personalized low latency communications. A method may include receiving a description of content of a message, receiving recipient data corresponding to at least two possible recipients within a population of possible recipients, and selecting a relevant subpopulation of the population. The selecting may include, for each of the at least two possible recipients, ranking a strength of an indirect relationship between the description and the recipient data. The indirect relationship may be based on the description, the recipient data and at least one additional data source. The selecting may also include, for each of the at least two possible recipients, adding a possible recipient to the relevant subpopulation based on the ranking of the indirect relationship associated with the possible recipient. The method may further include initiating a two-way communication channel between a sender of the message and the relevant subpopulation.

Abstract: A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries, wherein the private delta references previously-stored content. When a translation table has a private delta, its delta bit is set. The private delta is generated by analyzing a data buffer for content that is similar to previously-stored content.

Abstract: A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries, wherein the private delta references previously-stored content. When a translation table has a private delta, its delta bit is set. The private delta is generated by analyzing a data buffer for content that is similar to previously-stored content.

Abstract: Awareness of the relationships among the operating parameters for an individual core and among cores allows dynamic and intelligent management of the multi-core system. The relationships among operating parameters and cores, which can be somewhat opaque, are established with design-time simulations, and adapted with run time data collected from operation of the multi-core system. The relationships are expressed with functions that translate between operating parameters, between different cores, and between operating parameters of different cores. These functions are embodied in circuitry built into the multi-core system. The circuitry will be referred to hereinafter as a translator unit. The translator unit traverses the complex relational dependencies among multiple operating parameters and multiple cores, and determines an outcome with respect to one or more constraints corresponding to those operating parameters and cores.

Abstract: One aspect provides a method including: responsive to a request for data and a miss in both a first cache and a second cache, retrieving the data from memory, the first cache storing at least a subset of data stored in the second cache; inferring from information pertaining to the first cache a replacement entry in the second cache; and responsive to inferring from information pertaining to the first cache a replacement entry in the second cache, replacing an entry in the second cache with the data from memory. Other aspects are described and claimed.

Abstract: One aspect provides an apparatus including: at least one processor; and a computer readable storage medium having computer readable program code embodied therewith and executable by the at least one processor, the computer readable program code including: computer readable program code configured to, responsive to a request for data and a miss in both a first cache and a second cache, retrieve the data from memory, the first cache storing at least a subset of data stored in the second cache; computer readable program code configured to infer from information available from the first cache a replacement entry in the second cache; and computer readable program code configured to, responsive to inferring from information available from the first cache a replacement entry in the second cache, replace an entry in the second cache with the data from memory. Other aspects are described and claimed.

Abstract: A method for mirroring data between virtual machines includes intercepting a write command initiated from a virtual machine. Address and data information from the intercepted write command is stored within a queue located within a memory buffer of the primary server. The stored address and data information is transferred, upon filling the queue of the memory buffer of the primary server to a predetermined level, to a dedicated region of the memory of the primary server. The stored address and data information is sent from the dedicated region of the memory of the primary server to a backup server upon filling of the dedicated region of the memory of the primary server to a predetermined level.

Abstract: A system and method for providing quality of service during live migration includes determining one or more quality of service (QoS) specifications for one or more virtual machines (VMs) to be live migrated. Based on the one or more QoS specifications, a QoS is applied to a live migration of the one or more VMs by controlling resources including at least one of live migration network characteristics and VM execution parameters.

Abstract: A system and method for providing quality of service during live migration includes determining one or more quality of service (QoS) specifications for one or more virtual machines (VMs) to be live migrated. Based on the one or more QoS specifications, a QoS is applied to a live migration of the one or more VMs by controlling resources including at least one of live migration network characteristics and VM execution parameters.

Abstract: A computer implemented method creates a snapshot of a logical volume of a computer. The computer stores a system state of the computer in persistent memory. The computer flushes a cash of the computer. The computer identifies a preceding snapshot. Responsive to identifying the preceding snapshot, the computer hardens changes occurring after the preceding snapshot. The computer then switches from a first indirection table to a second indirection table.

Abstract: A computer implemented method creates a snapshot of a logical volume of a computer. The computer stores a system state of the computer in persistent memory. The computer flushes a cash of the computer. The computer identifies a preceding snapshot. Responsive to identifying the preceding snapshot, the computer hardens changes occurring after the preceding snapshot. The computer then switches from a first indirection table to a second indirection table.

Abstract: A method, system and computer program product are provided for implementing attachment of a user mode foreign device to a memory channel in a computer system. A user mode foreign device is attached to the memory channel using memory mapping of device registers and device buffers to the processor address space. The storage capacity on the device is doubly mapped in the address space creating separate control and data address spaces to allow user mode processes to control the device therefore eliminating the need for software system calls. A processor Memory Management Unit (MMU) coordinates multiple user processes accessing the device registers and buffers providing address space protection of each of interfaces, shifting device protection to the processor MMU from system software.

Abstract: A hash table method and structure comprises a processor that receives a plurality of access requests for access to a storage device. The processor performs a plurality of hash processes on the access requests to generate a first number of addresses for each access request. Such addresses are within a full address range. Hash table banks are operatively connected to the processor. The hash table banks form the storage device. Each of the hash table banks has a plurality of input ports. Specifically, each of the hash table banks has less input ports than the first number of addresses for each access request. The processor provides the addresses to the hash table banks, and each of the hash table banks stores pointers corresponding to a different limited range of addresses within the full address range (each of the different limited range of addresses is less than the full address range).

Abstract: Consistency of data stored in persistent memory is maintained using separate commit and harden operations for a transaction. A transaction is committed with a processing device, the committing including marking an end of an atomic operation on a modified object from the transaction, creating a new copy of the modified object, and storing a mapping of the modified object to the new copy of the modified object in a recorded log. A checksum identifying the modified object is created and stored in the recorded log. The transaction is hardened by storing the modified object and the recorded log from cache into persistent memory.