Abstract: A semiconductor device is provided. The semiconductor device includes a processing device that provides resource usage information including a utilization value; and a prediction information generating device that generates resource usage prediction information based on the resource usage information and provides the resource usage prediction information to the processing device. The prediction information generating device includes: an error calculator to calculate an error value between the utilization value and a predicted value included in the resource usage prediction information; a margin value calculator to receive the error value from the error calculator and calculate a margin value using the error value; an anchor value calculator to calculate an anchor value using the utilization value; and a predictor to output the predicted value using the anchor value and the margin value.

Abstract: A semiconductor device is provided. The semiconductor device includes a processing device that provides resource usage information including a utilization value; and a prediction information generating device that generates resource usage prediction information based on the resource usage information and provides the resource usage prediction information to the processing device. The prediction information generating device includes: an error calculator to calculate an error value between the utilization value and a predicted value included in the resource usage prediction information; a margin value calculator to receive the error value from the error calculator and calculate a margin value using the error value; an anchor value calculator to calculate an anchor value using the utilization value; and a predictor to output the predicted value using the anchor value and the margin value.

Abstract: A semiconductor device is provided. The semiconductor device includes a processing device that provides resource usage information including a utilization value; and a prediction information generating device that generates resource usage prediction information based on the resource usage information and provides the resource usage prediction information to the processing device. The prediction information generating device includes: an error calculator to calculate an error value between the utilization value and a predicted value included in the resource usage prediction information; a margin value calculator to receive the error value from the error calculator and calculate a margin value using the error value; an anchor value calculator to calculate an anchor value using the utilization value; and a predictor to output the predicted value using the anchor value and the margin value.

Abstract: A scheduling method includes calculating required performance for a given task, calculating use performance and real performance of a candidate processor, calculating power corresponding to the real performance, calculating expected energy usage of the candidate processor based on the required performance, the use performance, the real performance, and the calculated power and calculating performance efficiency of the candidate processor by considering a ratio of the expected energy usage to the real performance.

Abstract: A computing system includes an ISA identifier to identify an ISA (Instruction Set Architecture) of a task; a core selector to select a core having a highest power-performance efficiency among a plurality of cores based on the identified ISA; and a task allocator to allocate the task to the selected core.

Abstract: A semiconductor device is provided. The semiconductor device includes a processing device that provides resource usage information including a utilization value; and a prediction information generating device that generates resource usage prediction information based on the resource usage information and provides the resource usage prediction information to the processing device. The prediction information generating device includes: an error calculator to calculate an error value between the utilization value and a predicted value included in the resource usage prediction information; a margin value calculator to receive the error value from the error calculator and calculate a margin value using the error value; an anchor value calculator to calculate an anchor value using the utilization value; and a predictor to output the predicted value using the anchor value and the margin value.

Abstract: A scheduling method includes calculating required performance for a given task, calculating use performance and real performance of a candidate processor, calculating power corresponding to the real performance, calculating expected energy usage of the candidate processor based on the required performance, the use performance, the real performance, and the calculated power and calculating performance efficiency of the candidate processor by considering a ratio of the expected energy usage to the real performance.

Abstract: A computing system includes an ISA identifier to identify an ISA (Instruction Set Architecture) of a task; a core selector to select a core having a highest power-performance efficiency among a plurality of cores based on the identified ISA; and a task allocator to allocate the task to the selected core.

Abstract: An application processor including at least one core, at least one first cache respectively connected to the at least one core, the at least one first cache associated with an operation of the at least one core, a second cache associated with an operation of the at least one core, the second cache having a storage capacity greater than the first cache, a cache utilization management circuit configured to generate, a power control signal for power management of the application processor based on a cache hit rate of the second cache; and a power management circuit configured to determine, a power state level of the application processor based on the power control signal and an expected idle time, the power management circuit configured to control the at least one core, the at least one first cache, and the second cache based on the power state level may be provided.

Abstract: An application processor including at least one core, at least one first cache respectively connected to the at least one core, the at least one first cache associated with an operation of the at least one core, a second cache associated with an operation of the at least one core, the second cache having a storage capacity greater than the first cache, a cache utilization management circuit configured to generate, a power control signal for power management of the application processor based on a cache hit rate of the second cache; and a power management circuit configured to determine, a power state level of the application processor based on the power control signal and an expected idle time, the power management circuit configured to control the at least one core, the at least one first cache, and the second cache based on the power state level may be provided.