Abstract: A getter structure and method wherein a layer of seed material is deposited on a predetermined region of a surface of a structure under conditions to form a plurality of nucleation sites on a surface of the structure. The nucleation sites have an average height over the surface area of the predetermined region of less than one molecule thick. Subsequently a getter material is deposited over the surface to form a plurality of getter material members projecting outwardly from the nucleation sites.

Abstract: A getter structure and method wherein a layer of seed material is deposited on a predetermined region of a surface of a structure under conditions to form a plurality of nucleation sites on a surface of the structure. The nucleation sites have an average height over the surface area of the predetermined region of less than one molecule thick. Subsequently a getter material is deposited over the surface to form a plurality of getter material members projecting outwardly from the nucleation sites.

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract: A getter structure and method wherein a layer of seed material is deposited on a predetermined region of a surface of a structure under conditions to form a plurality of nucleation sites on a surface of the structure. The nucleation sites have an average height over the surface area of the predetermined region of less than one molecule thick. Subsequently a getter material is deposited over the surface to form a plurality of getter material members projecting outwardly from the nucleation sites.

Abstract: A method for forming a coating of material on selected portions of a surface of a substrate having a plurality of cavities, each cavity having outer, peripheral sidewalls extending outwardly from the surface. The method includes: providing a structure having a release agent thereon; contacting top surface of the wafer with the release agent to transfer portions of the release agent to the top surface of the wafer while bottom portions of the cavities remain spaced from the release agent to produce an intermediate structure; the release agent disposed on the top surface of the wafer and with the bottom portions of the cavities void of the release agent; exposing the intermediate structure to the material to blanket coat the material on both the release agent and the bottom portions of the cavities; and selectively removing the release agent together with the coating material while leaving the coating material on the bottom portions of the cavities.

Abstract: In certain embodiments, a bond gap control structure (BGCS) is placed outwardly from a substrate. The BGCS is configured to control a geometry of a bond line of a joining material. The joining material is deposited outwardly from the substrate. The substrate is bonded to another substrate with the joining material. The BGCS is at least partially removed from the substrate.

Abstract: A method for forming a coating of material on selected portions of a surface of a substrate having a plurality of cavities, each cavity having outer, peripheral sidewalls extending outwardly from the surface. The method includes: providing a structure having a release agent thereon; contacting top surface of the wafer with the release agent to transfer portions of the release agent to the top surface of the wafer while bottom portions of the cavities remain spaced from the release agent to produce an intermediate structure; the release agent disposed on the top surface of the wafer and with the bottom portions of the cavities void of the release agent; exposing the intermediate structure to the material to blanket coat the material on both the release agent and the bottom portions of the cavities; and selectively removing the release agent together with the coating material while leaving the coating material on the bottom portions of the cavities.

Abstract: A method of forming a window cap wafer (WCW) structure for semiconductor devices includes machining a plurality of cavities into a front side of a first substrate; bonding the first substrate to a second substrate, at the front side of the first substrate; removing a back side of the first substrate so as to expose the plurality of cavities, thereby defining the WCW structure comprising the second substrate and a plurality of vertical supports comprised of material of the first substrate.

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract: In certain embodiments, a system includes a deposition system and a plasma/bonding system. The deposition system deposits a solder outwardly from a substrate of a number of substrates. The plasma/bonding system comprises a plasma system configured to plasma clean the substrate and a bonding system configured to bond the substrates. The plasma/bonding system at least reduces reoxidation of the solder. In certain embodiments, a method comprises depositing solder outwardly from a substrate, removing metal oxide from the substrate, and depositing a capping layer outwardly from the substrate to at least reduce reoxidation of the solder.

Abstract: In accordance with particular embodiments, a method for packaging an incident radiation detector includes depositing an opaque solder resistant material on a first surface of a transparent lid substrate configured to cover at least one detector. The method also includes forming at least one cavity in the lid substrate. The method further includes forming a first portion of at least one hermetic seal ring on the opaque solder resistant material. The first portion of each hermetic seal ring surrounds a perimeter of a corresponding cavity in the lid substrate. The method also includes aligning the first portion of the at least one hermetic seal ring with a second portion of the at least one hermetic seal ring. The method additionally includes bonding the first portion of the at least one hermetic seal ring with the second portion of the at least one hermetic seal ring with solder.

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract: A wafer level vacuum packaged (WLVP) device having a first substrate having an array of detectors and a second substrate bonded to the first substrate having a plurality of protrusions and a plurality of getter material members projecting outwardly from a sidewall of the protrusions members are disposed at oblique angles to the sidewalls and have ends extending into gaps between the protrusions. The device is formed by: forming protrusions into a surface of a substrate; and depositing getter material by physical vapor deposition from an evaporating source of the getter material at an oblique angle to the sidewalls, atoms of the getter material initially forming nucleation sites on the sidewalls with subsequent atoms attaching to the nucleation sites and shadowing area surrounding each nucleation site, the getter material thereby growing into structures towards the evaporating source.

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract: A method of forming a window cap wafer (WCW) structure for semiconductor devices includes machining a plurality of cavities into a front side of a first substrate; bonding the first substrate to a second substrate, at the front side of the first substrate; removing a back side of the first substrate so as to expose the plurality of cavities, thereby defining the WCW structure comprising the second substrate and a plurality of vertical supports comprised of material of the first substrate.

Abstract: In certain embodiments, a bond gap control structure (BGCS) is placed outwardly from a substrate. The BGCS is configured to control a geometry of a bond line of a joining material. The joining material is deposited outwardly from the substrate. The substrate is bonded to another substrate with the joining material. The BGCS is at least partially removed from the substrate.

Abstract: In certain embodiments, a bond gap control structure (BGCS) is placed outwardly from a substrate. The BGCS is configured to control a geometry of a bond line of a joining material. The joining material is deposited outwardly from the substrate. The substrate is bonded to another substrate with the joining material. The BGCS is at least partially removed from the substrate.

Abstract: In accordance with particular embodiments, a method for packaging electronic devices includes melting solder for a solder jet. The method additionally includes depositing the melted solder from the solder jet in a pattern on a first substrate of a first component of an electronic device. The pattern comprises a plurality of individual dots of melted solder. The method also includes aligning a second substrate of a second component of the electronic device with the pattern deposited on the first substrate of the electronic device. The method further includes re-melting the solder deposited in the pattern on the first substrate. The method additionally includes, while the solder is re-melting, compressing the first and second substrates.