Patents by Inventor Byeong-Cheol Lim

Byeong-Cheol Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240149751
    Abstract: A dual release actuator for a vehicle seat includes a motor, a cable carrier configured to receive power of the motor, thereby rotating to selectively pull one of two different cables, a Hall sensor to sense rotation of the motor, and a controller configured to count a sensing pulse of the Hall sensor for controlling rotation of the motor.
    Type: Application
    Filed: May 17, 2023
    Publication date: May 9, 2024
    Inventors: Jae Wook Kim, Sang Soo Lee, Deok Soo Lim, Hyun Wook Lim, Sang Ho Lee, Sang Hark Lee, Hak Cheol Lee, Deok Ki Kim, Byeong Deok Choi, Hoe Cheon Kim, Hwa Young Mun, Seung Yeop Lee, Cheol Hwan Yoon, Jung Bin Lee, Byung Ju Kang
  • Patent number: 11942264
    Abstract: A coil component includes a body having a first surface, and a first end surface and a second end surface connected to the first surface and opposing each other in a length direction; a support substrate disposed inside the body; a coil portion comprising a first coil pattern and first and second lead-out patterns, each disposed on a first surface of the support substrate; first and second slit portions, respectively defined on edge portions of the first surface of the body to expose the first and second lead-out patterns; and first and second external electrodes disposed on the first and second slit portions to be connected to the first and second lead-out patterns. At least one of the first and second lead-out patterns has a thickness greater than a thickness of each of the first coil pattern and the first dummy lead-out pattern.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: March 26, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: No Il Park, Byung Soo Kang, Seung Mo Lim, Byeong Cheol Moon, Boum Seock Kim, Yong Hui Li, Seung Min Lee
  • Patent number: 11915853
    Abstract: A coil component is provided. The coil component includes a body having fifth and sixth surfaces opposing each other, first and second surfaces respectively connecting the fifth and sixth surfaces of the body and opposing each other, and third and fourth surfaces respectively connecting the first and second surfaces of the body and opposing each other in one direction, a recess disposed in an edge between one of the first and second surfaces of the body and the sixth surface of the body, a coil portion disposed inside the body and exposed through the recess, and an external electrode including a connection portion disposed in the recess and connected to the coil portion, and a pad portion disposed on one surface of the body. A length of the pad portion in the one direction is greater than a length of the connection portion in the one direction.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: February 27, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung Mo Lim, Seung Min Lee, Byeong Cheol Moon, Yong Hui Li, Byung Soo Kang, Ju Hwan Yang, Tai Yon Cho, No Il Park, Tae Jun Choi
  • Patent number: 7932149
    Abstract: In a method of manufacturing a semiconductor device, a tunnel insulation layer is formed on a substrate. A charge trapping layer is formed on the tunnel insulation layer. A protection layer pattern or a mold is formed on the charge trapping layer. Charge trapping layer patterns are formed on the tunnel insulation layer by etching the charge trapping layer using the protection layer pattern or the mold. The charge trapping layer patterns may be spaced apart from each other. Blocking layers are formed on the charge trapping layer patterns, respectively. A gate electrode is formed on the blocking layers and the tunnel insulation layer using the protection layer pattern or the mold.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: April 26, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyun Park, Jeong-Uk Han, Jae-Min Yu, Young-Cheon Jeong, Sang-Hoon Park, Kwan-Jong Roh, Byeong-Cheol Lim, Yong-Seok Chung
  • Publication number: 20090286369
    Abstract: In a method of manufacturing a semiconductor device, a tunnel insulation layer is formed on a substrate. A charge trapping layer is formed on the tunnel insulation layer. A protection layer pattern or a mold is formed on the charge trapping layer. Charge trapping layer patterns are formed on the tunnel insulation layer by etching the charge trapping layer using the protection layer pattern or the mold. The charge trapping layer patterns may be spaced apart from each other. Blocking layers are formed on the charge trapping layer patterns, respectively. A gate electrode is formed on the blocking layers and the tunnel insulation layer using the protection layer pattern or the mold.
    Type: Application
    Filed: May 19, 2009
    Publication date: November 19, 2009
    Inventors: Jee-Hyun Park, Jeong-Uk Han, Jae-Min Yu, Young-Cheon Jeong, Sang-Hoon Park, Kwan-Jong Roh, Byeong-Cheol Lim, Yong-Seok Chung
  • Publication number: 20080050875
    Abstract: A method of fabricating a compound device includes forming a first gate insulating pattern on a semiconductor substrate including a first region and a second region, forming a second gate insulating layer on the first gate insulating pattern, and after forming the second gate insulating layer, forming a well in the second region of the semiconductor substrate.
    Type: Application
    Filed: December 27, 2006
    Publication date: February 28, 2008
    Inventors: Jung-Ho Moon, Chul-Soon Kwon, Jae-Min Yu, Young-Cheon Jeong, In-Gu Yoon, Byeong-Cheol Lim
  • Publication number: 20070200165
    Abstract: Example embodiments may provide a nonvolatile memory device. The example embodiment nonvolatile memory device may include a floating gate structure formed on a semiconductor substrate with a gate insulating layer between them and/or a control gate formed adjacent to the floating gate with a tunneling insulation layer between them. The floating gate may include a first floating gate formed on the gate insulating layer, a second floating gate formed on the first floating gate with a first insulating pattern between them, and/or a gate connecting layer formed on at least one sidewall of the first insulating pattern so that the gate conducting layer may electrically connect the first floating gate and the second floating gate. The second floating gate may have a tip formed at its longitudinal end that may not contact the gate connecting layer.
    Type: Application
    Filed: January 23, 2007
    Publication date: August 30, 2007
    Inventors: Young-Cheon Jeong, Chul-Soon Kwon, Jae-Min Yu, Jae-Hyun Park, Jung-Ho Moon, Soung-Youb Ha, Byeong-Cheol Lim