Abstract: A clock signal generating method includes receiving a duty code that represents a duty of a clock signal, and a period code that represents a period of a clock signal, and normalizing the duty code to the period code to output a normalized duty code. The clock signal generating method further includes controlling a rising timing of a clock signal in response to the period code, and controlling a falling timing of the clock signal in response to the normalized duty code to generate a timing-controlled clock signal.

Abstract: A low-dropout regulator comprises an analog-to-digital converter that converts a feedback analog voltage signal into a digital signal, a phase synthesizing unit that generates a first control signal having a pulse width corresponding to error information in the digital signal by performing phase synthesis according to clock skew control, a charge pump circuit that selects a charge loop or a discharge loop based on polarity information in the digital signal, and generates an output control voltage according to current that flows during a period corresponding to the pulse width of the first control signal in the selected loop, and an output circuit that generates an output voltage based on an input voltage and the output control voltage, and generates the feedback analog voltage signal based on the output voltage.

Abstract: A low-dropout regulator comprises an analog-to-digital converter that converts a feedback analog voltage signal into a digital signal, a phase synthesizing unit that generates a first control signal having a pulse width corresponding to error information in the digital signal by performing phase synthesis according to clock skew control, a charge pump circuit that selects a charge loop or a discharge loop based on polarity information in the digital signal, and generates an output control voltage according to current that flows during a period corresponding to the pulse width of the first control signal in the selected loop, and an output circuit that generates an output voltage based on an input voltage and the output control voltage, and generates the feedback analog voltage signal based on the output voltage.

Abstract: A digital-to-analog conversion apparatus to convert a digital signal to an output analog voltage signal includes an analog-to-digital conversion processing circuit and an analog voltage signal output circuit. The analog-to-digital conversion processing circuit is configured to increase a resolution of the digital-to-analog conversion apparatus without increasing a frequency of an input clock signal. The analog voltage signal output circuit is configured to generate the output analog voltage signal based on the input clock signal at the increased resolution of the digital-to-analog conversion apparatus.

Abstract: A digital-to-analog conversion apparatus to convert a digital signal to an output analog voltage signal includes an analog-to-digital conversion processing circuit and an analog voltage signal output circuit. The analog-to-digital conversion processing circuit is configured to increase a resolution of the digital-to-analog conversion apparatus without increasing a frequency of an input clock signal. The analog voltage signal output circuit is configured to generate the output analog voltage signal based on the input clock signal at the increased resolution of the digital-to-analog conversion apparatus.

Abstract: A clock signal generating method includes receiving a duty code that represents a duty of a clock signal, and a period code that represents a period of a clock signal, and normalizing the duty code to the period code to output a normalized duty code. The clock signal generating method further includes controlling a rising timing of a clock signal in response to the period code, and controlling a falling timing of the clock signal in response to the normalized duty code to generate a timing-controlled clock signal.

Abstract: A frequency divider includes a prescaler and multiple modulus dividers commonly coupled to the prescaler. The prescaler generates intermediate frequency signals having a same phase difference with respect to one another in response to an oscillation frequency signal. The prescaler operates at a first frequency. The modulus dividers respectively divide the intermediate frequency signals with respective ratio to provide a plurality of division frequency signals in response to a control signal. The modulus dividers operate at a second frequency less than the first frequency.

Abstract: A programmable variable gain amplifier includes at least three amplifiers. A first amplifier is configured to amplify an input signal. A second amplifier, which includes a programmable output load stage, is configured to receive an output signal from the first amplifier and to output a first differential output signal. The output load stage includes multiple first switches and multiple first diode-connected transistors that are open-circuited or short-circuited by the first switches. A third amplifier, which includes a programmable current mirror input stage, is configured to receive the first differential output signal from the second amplifier through the current mirror input stage and to output a second differential output signal. The current mirror input stage includes multiple second switches and multiple second transistors that are open-circuited or short-circuited by the plurality of second switches.

Abstract: A frequency divider includes a prescaler and multiple modulus dividers commonly coupled to the prescaler. The prescaler generates intermediate frequency signals having a same phase difference with respect to one another in response to an oscillation frequency signal. The prescaler operates at a first frequency. The modulus dividers respectively divide the intermediate frequency signals with respective ratio to provide a plurality of division frequency signals in response to a control signal. The modulus dividers operate at a second frequency less than the first frequency.

Abstract: A gain controllable wide-band low noise amplifier includes a first transistor coupled to an input node and an output node and amplifying an input signal to generate an output signal, a second transistor allowing the output signal to feedback to the input node, and a control circuit complementarily controlling transconductance of the first and second transistors.

Abstract: A programmable variable gain amplifier includes at least three amplifiers. A first amplifier is configured to amplify an input signal. A second amplifier, which includes a programmable output load stage, is configured to receive an output signal from the first amplifier and to output a first differential output signal. The output load stage includes multiple first switches and multiple first diode-connected transistors that are open-circuited or short-circuited by the first switches. A third amplifier, which includes a programmable current mirror input stage, is configured to receive the first differential output signal from the second amplifier through the current mirror input stage and to output a second differential output signal. The current mirror input stage includes multiple second switches and multiple second transistors that are open-circuited or short-circuited by the plurality of second switches.

Abstract: A gain controllable wide-band low noise amplifier includes a first transistor coupled to an input node and an output node and amplifying an input signal to generate an output signal, a second transistor allowing the output signal to feedback to the input node, and a control circuit complementarily controlling transconductance of the first and second transistors.

Abstract: A PLL-based CMOS fractional-N frequency synthesizer, which has an on-chip LC Voltage Controlled Oscillator. A higher-order discrete sigma-delta modulator is used in the fractional-N frequency synthesizer resulting in a strong attention at low frequencies for quantization noise. The synthesizer employs a noise shaping method to suppress fractional spurs using the high-order sigma-delta modulator.