Abstract: Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region.

Abstract: A semiconductor device includes a substrate including a first impurity diffusion region having a first doping concentration and at least one second impurity diffusion region having a second doping concentration different from the first doping concentration, the at least one second impurity region being surrounded by the first impurity diffusion region; at least one electrode facing the first impurity diffusion region and the at least one second impurity diffusion region; and at least one insulating layer between the first impurity diffusion region and the at least one electrode, and between the at least one second impurity diffusion region and the at least one electrode.

Abstract: Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region.

Abstract: Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region.

Abstract: A semiconductor device includes a substrate including a first impurity diffusion region having a first doping concentration and at least one second impurity diffusion region having a second doping concentration different from the first doping concentration, the at least one second impurity region being surrounded by the first impurity diffusion region; at least one electrode facing the first impurity diffusion region and the at least one second impurity diffusion region; and at least one insulating layer between the first impurity diffusion region and the at least one electrode, and between the at least one second impurity diffusion region and the at least one electrode.

Abstract: Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region.

Abstract: Methods of fabricating CMOS transistors are disclosed. A disclosed method includes forming first and second gate patterns on the first and second wells, respectively; forming a sidewall insulating layer over the substrate; forming first lightly doped regions in the first well by NMOS LDD ion implantation; forming a first gate spacer insulating layer over the substrate; forming second lightly doped regions in the second well by PMOS LDD ion implantation; sequentially stacking a spacer insulating layer and a second gate spacer insulating layer on the first gate spacer insulating layer; forming first and second spacers on sidewalls of the first and second gate patterns; and forming first and second heavily doped regions in the first and second wells by NMOS and PMOS source/drain ion implantations, respectively.

Abstract: Example embodiments relate to a semiconductor device and a method of fabricating the same. A dummy pattern may be formed on a semiconductor substrate. Source and drain regions may be formed on the semiconductor substrate at sides of the dummy pattern. A first metal silicide layer may be formed on the source and drain regions. A recess region may be formed in the semiconductor substrate under the dummy pattern. A gate insulating layer and a gate electrode may be formed in the recess region.

Abstract: A method of fabricating a fin transistor is disclosed. An example method stacks a mask oxide layer and a nitride layer on a semiconductor substrate, forms a fin by etching the nitride and mask oxide layers and silicon, forms an insulating oxide layer, and forms a gate electrode by etching the insulating oxide layer corresponding to a gate forming area using a gate mask, by forming a gate oxide layer on a sidewall of the silicon exposed by the etch and burying a metal. The example method also removes the remaining insulating oxide layer using an etch rate difference, forms a gate spacer, and forms source/drain regions in the silicon substrate to be aligned with the gate electrode. Additionally, the example method forms a second insulating oxide layer over the substrate, etches the second insulating oxide layer using a metal mask, forms contact holes on the source/drain regions, respectively, and fills the contact holes and the portion etched via the metal mask with a metal.

Abstract: A method of forming a salicide pattern for measuring junction leakage current is disclosed. An example method forms device isolation structures on a silicon substrate, forms a well region between the device isolation structures, forms source and drain regions on the well region, and forms a salicide layer on the source and drain regions. The example method also removes some part of the salicide layer, deposits an interlayer dielectric layer on the salicide layer, and forms via holes in the interlayer dielectric layer and filling metal into the via holes to form a via. The example method further planarizes the interlayer dielectric layer and the via, and forms metal interconnects on the interlayer dielectric layer.

Abstract: A method of fabricating a fin field effect transistor is disclosed. An example method forms a thermal oxide layer as a hard mask for etching a silicon fin on an SOI substrate, transcribes a fin pattern, forms a fin FET body by etching using the fin pattern as an etch mask, and restores a sidewall damaged by the etching remove a sacrificial silicon oxide layer. The example method also deposits a high-K dielectric as a gate dielectric, deposits a metal layer, planarizes the metal layer to a height of a hard oxide, forms a nitride layer on the planarized metal layer, and patterns the nitride layer using a hard mask for forming a pattern to form a nitride layer pattern. Additionally, the example method forms a metal gate using the nitride layer pattern, removes a remaining hard oxide mask, and grows a sidewall oxide layer on the metal gate.

Abstract: A method of forming device isolation structures in an embedded semiconductor device is disclosed. The method of forming device isolation structures comprises the steps of: providing a substrate having a first area in which ions are implanted; forming a first device isolation structure through partial oxidation in the first area; forming a first type well with deep junction by diffusing the ions in the first area; forming a second device isolation structure with a trench in a second area of the substrate; forming a first type well with shallow junction in peripheral regions of the second device isolation structure and a region between the first device isolation structure and the second device isolation structure; forming a second type well with shallow junction in peripheral regions of the first device isolation structure and a region of the second device isolation structure; and defining first and second type active regions on the substrate.

Abstract: The present invention relates to a method for fabricating semiconductor devices having triple wells, the present invention has an effect as follows. The present invention provides carrying out N-well and P-well and R-well ion implantation using a mask for implanting two wells after forming an element isolation oxide film, defining an accurate well region by forming wells having an accurate profile due to activating impurity ions in accordance with the thermal process, and improving the punch characteristic between a well and a well.