Patents by Inventor Byron A. Alcorn

Byron A. Alcorn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6943804
    Abstract: Systems and methods are provided for performing a BLT (BLock Transfer). In accordance with one embodiment, a method uses a texture-mapping subsystem to perform the BLT by configuring the texture-mapping subsystem with coordinate values corresponding to a block of pixels to be transferred. In accordance with another embodiment, an apparatus comprises logic for defining a texture map from a source segment of memory corresponding to a frame buffer, logic for configuring a texture-mapping subsystem with coordinate values corresponding to a first block of pixels on a display, logic for using a texture-mapping subsystem to apply the texture map defined by the configured coordinate values to a destination segment of memory corresponding to a second block of pixels on the graphic display, wherein the application of the texture map effects a BLT of the data from the first block of pixels to the second block of pixels.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: September 13, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Byron A. Alcorn, Ronald D. Larson, Larry Jay Thayer
  • Publication number: 20050190192
    Abstract: A system is described that is broadly directed to a system of integrated circuit components. The system comprises a plurality of nodes that are interconnected by communication links. A random access memory (RAM) is connected to each node. At least one functional unit is integrated into each node, and each functional unit is configured to carry out a predetermined processing function. Finally, each RAM includes a coherency mechanism configured to permit only read access to the RAM by other nodes, the coherency mechanism further configured to permit write access to the RAM only by functional units that are local to the node.
    Type: Application
    Filed: May 3, 2005
    Publication date: September 1, 2005
    Inventors: Darel Emmot, Byron Alcorn
  • Patent number: 6933943
    Abstract: A distributed resource system comprises a plurality of compute resource units operable to execute graphics applications and generate graphics data, and a plurality of visualization resource units communicatively coupled to the plurality of compute resource units and operable to render pixel data from the graphics data. A first network couples a network compositor to the plurality of visualization resource units. The network compositor is operable to synchronize the received pixel data from the plurality of visualization resource units and receive the pixel data from the visualization resource units and to composite the synchronized pixel data into at least one image. A plurality of display devices, at least one of which is located remotely from the plurality of compute resource units, are coupled to the network compositor and operable to display the at least one image.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: August 23, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Byron A. Alcorn
  • Publication number: 20050174353
    Abstract: A centralized resource system comprises a plurality of compute resource units, a plurality of visualization resource units, and a switching fabric coupling the plurality of visualization resource units to the plurality of compute resource units. The switching fabric is operable to couple select one or more visualization resource units to select one or more compute resource units for generating at least one graphical image. A plurality of display devices is coupled to the one or more select visualization resource units operable to display the at least one graphical image.
    Type: Application
    Filed: April 15, 2005
    Publication date: August 11, 2005
    Inventors: Byron Alcorn, Kevin Lefebvre
  • Patent number: 6919894
    Abstract: A system is described that is broadly directed to a system of integrated circuit components. The system comprises a plurality of nodes that are interconnected by communication links. A random access memory (RAM) is connected to each node. At least one functional unit is integrated into each node, and each functional unit is configured to carry out a predetermined processing function. Finally, each RAM includes a coherency mechanism configured to permit only read access to the RAM by other nodes, the coherency mechanism further configured to permit write access to the RAM only by functional units that are local to the node.
    Type: Grant
    Filed: July 21, 2003
    Date of Patent: July 19, 2005
    Assignee: Hewlett Packard Development Company, L.P.
    Inventors: Darel N. Emmot, Byron A. Alcorn
  • Patent number: 6909432
    Abstract: A centralized resource system comprises a plurality of compute resource units, a plurality of visualization resource units, and a switching fabric coupling the plurality of visualization resource units to the plurality of compute resource units. The switching fabric is operable to couple select one or more visualization resource units to select one or more compute resource units for generating at least one graphical image. A plurality of display devices is coupled to the one or more select visualization resource units operable to display the at least one graphical image.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: June 21, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Byron A. Alcorn, Kevin T. Lefebvre
  • Patent number: 6891548
    Abstract: Systems and methods provide a more efficient and effective gradient computation. Specifically, in one embodiment, a method is provided for calculating a texture-mapping gradient, which comprises calculating constant values for use in a gradient-calculating equation, passing the constant values to logic configured to calculate the gradient, and computing the gradient using barycentric coordinates and the calculated constant values. In accordance with another embodiment, an apparatus is provided for calculating a texture-mapping gradient, which comprises logic for calculating constant values for use in a gradient-calculating equation, and logic for computing the gradient-calculating equation using barycentric coordinates and the calculated constant values. In accordance with another embodiment, a computer-readable medium is also provided that contains code (e.g., RTL logic) for generating the computational logic mentioned above.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: May 10, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Byron Alcorn, Jason Kassoff
  • Patent number: 6891533
    Abstract: Methods and apparatus for compositing separately generated three-dimensional images in a two-dimensional graphics imaging pipeline of a computer graphics system to ultimately render a composited image on a display screen. The computer graphics system includes generally a graphics library and graphics hardware together defining the imaging pipeline, and a graphics application program invoking operations in the imaging pipeline through an application program interface provided by the graphics library. The imaging pipeline may be the only pipeline in the graphics system or it may be part of a larger rendering pipeline that also includes a geometric pipeline that generates two-dimensional images represented by pixel data. The graphics system also includes a frame buffer for storing pixel data to be displayed on the display device. The image compositing module performs depth testing and stencil testing on specific components of the next image that are separately and sequentially processed by the imaging pipeline.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: May 10, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Byron A Alcorn, Jon L Ashburn
  • Patent number: 6882346
    Abstract: A graphical display system utilizes a plurality of graphics pipelines to render data to a display device. More specifically, the graphical display system utilizes a first graphics pipeline, a second graphics pipeline, a compositor, and a display device. The first graphics pipeline renders a first portion of a graphical command, and the second graphics pipeline renders a second portion of a graphical command. The compositor receives the first and second portions of graphical data and interfaces the first and second portions with the display device. The display device then displays an image based on the first and second portions of graphical data respectively rendered by the first and second graphics pipelines. By enabling a plurality of graphics pipelines to render different portions of graphical data to the same display device, the speed and/or image quality associated with the image displayed by the display device can be improved.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: April 19, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kevin Lefebvre, Don B. Hoffman, Joseph Norman Gee, Jeffrey J Walls, Byron A Alcorn
  • Patent number: 6873331
    Abstract: The present invention is broadly directed to a system of components defining a plurality of nodes and a random access memory (RAM) connected to each node. The system comprises at least one producer functional unit configured to perform a predetermined processing function resulting in the creation of at least one producer message, a communication mechanism configured to manage and control communication of messages with other nodes, at least one pointer that is configurable to point to a storage location within the RAM, and a message logic configured to interpret content of the at least one producer message, the message logic further configured to associate the producer message with a subset of the at least one pointers based upon the content of the at least one producer message, the message logic further configured to store the at least one producer message within the RAM at the locations indicated by the associated subset of at least one pointer.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: March 29, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Darel N. Emmot, Byron A. Alcorn
  • Patent number: 6870539
    Abstract: A preferred device for producing a composite digital video data stream containing pixel data corresponding to an image to be rendered includes an input mechanism which is configured to receive multiple digital video data streams from graphics pipelines. In response to receiving a first of the multiple digital video data streams, the input mechanism provides a frame of data corresponding to the image to be rendered and inserts pixel data from the multiple digital video data streams into the frame of data, thereby forming at least a portion of the composite digital video data stream.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: March 22, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: K Scott Bower, Byron A Alcorn, Joseph Norman Gee, Kevin Lefebvre
  • Patent number: 6864895
    Abstract: The pseudo-linear frame buffer mapping system and method facilitates the clearing of the frame buffer memory of a graphics display system by subdividing the region of the frame buffer which is to be cleared into a plurality of sub-regions and by initiating the clear command concurrently to each of the plurality of sub-regions.
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: March 8, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kendall F Tidwell, Courtney Goeltzenleuchter, Theodore G Rossin, Byron A Alcorn
  • Publication number: 20050044288
    Abstract: A system and method communicate information from a single-threaded application over multiple I/O busses to a computing subsystem for processing. In accordance with one embodiment, a method is provided that partitions state-sequenced information for communication to a computer subsystem, communicates the partitioned information to the subsystem over a plurality of input/output busses, and separately processes the information received over each of the plurality of input/output busses, without first se-sequencing the information.
    Type: Application
    Filed: August 20, 2003
    Publication date: February 24, 2005
    Inventors: Darel Emmot, Byron Alcorn, Ronald Larson
  • Patent number: 6853380
    Abstract: A graphical display system utilizes a plurality of graphics pipelines, a compositor, and application interface logic. The plurality of graphics pipelines are configured to render graphical data in parallel. The compositor is configured to define a composite data signal that is based on the graphical data rendered by each of the pipelines. The application interface logic is configured to retrieve configuration data indicative of a configuration of the compositor. The application interface logic is further configured to provide the configuration data to a graphics application, wherein the graphics application is configured to provide graphical data to the plurality of pipelines based on the configuration data.
    Type: Grant
    Filed: March 4, 2002
    Date of Patent: February 8, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Byron A. Alcorn
  • Publication number: 20040179007
    Abstract: A node of a network for generating image frames comprising a graphics device operable to generate a viewable data set and a non-viewable data set representative of a three-dimensional image frame, and a first output interface operable to transmit the non-viewable data set is provided. A network for generating image frames comprising a plurality of rendering nodes operable to respectively generate a viewable data set and a non-viewable data set, and further operable to transmit the viewable and non-viewable data sets, and a compositor interconnected with the plurality of rendering nodes and operable to respectively receive the viewable and non-viewable data sets from the plurality of rendering nodes and operable to assemble a composite image from the viewable and non-viewable data sets is provided.
    Type: Application
    Filed: March 14, 2003
    Publication date: September 16, 2004
    Inventors: K. Scott Bower, Byron A. Alcorn, Courtney D. Goeltzenleuchter, Kevin T. Lefebvre, James A. Schinnerer
  • Patent number: 6791553
    Abstract: A graphical display system utilizes a plurality of graphics pipelines to efficiently display a jitter enhanced image. More specifically, the graphical display system utilizes a plurality of graphical pipelines, a compositor, and a display device. Each of the graphical pipelines receives and renders graphical data. In rendering the graphical data, each of the graphical pipelines mathematically combines a different offset to coordinate values included within the graphical data. The compositor receives the graphical data rendered by the plurality of pipelines and blends color values associated with corresponding coordinate values within the graphical data. The compositor also interfaces the blended color values with the display device, which displays an image based on at least the blended color values. As a result, graphical data defining a jitter enhanced image is efficiently rendered to the display device.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: September 14, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kevin Lefebvre, Don B. Hoffman, Byron A Alcorn, Joseph Norman Gee
  • Publication number: 20040085322
    Abstract: Systems and methods are provided for performing a BLT (BLock Transfer). In accordance with one embodiment, a method uses a texture-mapping subsystem to perform the BLT by configuring the texture-mapping subsystem with coordinate values corresponding to a block of pixels to be transferred. In accordance with another embodiment, an apparatus comprises logic for defining a texture map from a source segment of memory corresponding to a frame buffer, logic for configuring a texture-mapping subsystem with coordinate values corresponding to a first block of pixels on a display, logic for using a texture-mapping subsystem to apply the texture map defined by the configured coordinate values to a destination segment of memory corresponding to a second block of pixels on the graphic display, wherein the application of the texture map effects a BLT of the data from the first block of pixels to the second block of pixels.
    Type: Application
    Filed: October 30, 2002
    Publication date: May 6, 2004
    Inventors: Byron A. Alcorn, Ronald D. Larson, Larry Jay Thayer
  • Patent number: 6724396
    Abstract: Methods and apparatus are provided for allocating correlated data sets, such as texture data, among first and second areas of memory in a computer graphics system. Each texture map in a series of texture maps is divided into a set of blocks of data. Each texture map that has a width greater than one block is divided into first and second map areas. Typically, the first and second map areas are the left and right halves of each texture map. Blocks of data from the first map areas of odd level texture maps are stored in the first memory area, blocks of data from the second map areas of even level texture maps are stored in the first memory area, blocks of data from the second map areas of odd level texture maps are stored in the second memory area and blocks of data from the first map areas of even level texture maps are stored in the second memory area. The blocks of data representing each texture map in the series of texture maps are stored in consecutive blocks of memory.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: April 20, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Darel N Emmot, Byron A Alcorn
  • Patent number: 6707453
    Abstract: A rasterizer implementing a single edge stepping interpolator to interpolate both diffuse and specular lighting components across an edge of the primitive, and/or a single span stepping interpolator to interpolate both diffuse and specular lighting components across the spans of the primitive. When the edge or span being interpolated includes a non-negligible specular lighting component, the diffuse and specular lighting components are separately and successively rasterized. Otherwise, only the diffuse lighting component is interpolated over the edge or span.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: March 16, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Theodore G Rossin, Byron A Alcorn
  • Publication number: 20040036692
    Abstract: Systems and methods provide a more efficient and effective gradient computation. Specifically, in one embodiment, a method is provided for calculating a texture-mapping gradient, which comprises calculating constant values for use in a gradient-calculating equation, passing the constant values to logic configured to calculate the gradient, and computing the gradient using barycentric coordinates and the calculated constant values. In accordance with another embodiment, an apparatus is provided for calculating a texture-mapping gradient, which comprises logic for calculating constant values for use in a gradient-calculating equation, and logic for computing the gradient-calculating equation using barycentric coordinates and the calculated constant values. In accordance with another embodiment, a computer-readable medium is also provided that contains code (e.g., RTL logic) for generating the computational logic mentioned above.
    Type: Application
    Filed: August 23, 2002
    Publication date: February 26, 2004
    Inventors: Byron Alcorn, Jason Kassoff