Patents by Inventor Byron B. Siu

Byron B. Siu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process for forming MOS transistor with buried oxide regions for insulation
    Patent number: 4700454
    Abstract: MOS process for forming field-effect devices in self-alignment with a buried oxide region. Oxygen is implanted in alignment with masking members after gates have been defined from the masking members. The masking members block the oxygen implantation and thus the channel regions of subsequently formed transistors are self-aligned with openings in the buried oxide layer.
    Type: Grant
    Filed: November 4, 1985
    Date of Patent: October 20, 1987
    Assignee: Intel Corporation
    Inventors: William Baerg, Chiu H. Ting, Byron B. Siu, J. C. Tzeng