Abstract: A non-volatile memory device includes an output driver to output a data signal. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.

Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

Abstract: A memory system and a buffer device include a structure for performing training operations for a plurality of memory devices to ensure data reliability. A memory controller is configured to control a memory operation for a plurality of memory devices. A memory module includes the plurality of memory devices and a buffer device connected between the memory devices and the memory controller. Training operations for the memory devices to be performed by the buffer device including a training block with a signal delay circuit, and the memory controller performs the training operations by controlling the training block.

Abstract: A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.

Abstract: A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.

Abstract: An equalizer circuit may include an equalizer controller and a plurality of equalizers. The equalizer controller may prove separate sets of enable signals, delay control signals and voltage control signals to the separate equalizers based on a control signal. The equalizers provide equalizer signals to separate connection nodes between separate pairs of logic circuits. An equalizer may be selectively activated based on a received enable signal. An equalizer may include a delay control circuit and a voltage control circuit. The delay control circuit may delay a received transfer signal to generate a delayed transfer signal based on a received delay control signal. The voltage control circuit may generate an equalizer signal based on the delayed transfer signal and a received voltage control signal. The equalizer circuit may reduce inter-symbol interference in the integrated circuit based on providing the equalizer signals to the connection nodes between the logic circuits.

Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

Abstract: A semiconductor chip, a test system, and a method of testing the semiconductor chip. The semiconductor chip includes a pulse generator configured to generate a test pulse in response to a test request; a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).

Abstract: A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.

Abstract: A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.

Abstract: A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.

Abstract: A reception interface circuit includes a termination circuit, a buffer and an interface controller. The termination circuit is configured to change a termination mode in response to a termination control signal. The buffer is configured to change a reception characteristic in response to a buffer control signal. The interface controller is configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode. The reception interface circuit may support various communication standards by changing the reception characteristic of the buffer in association with the termination mode. Using the reception interface circuit, communication efficiency of transceiver systems such as a memory system and/or compatibility between a transmitter device and a receiver device may be improved.

Abstract: A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.

Abstract: A semiconductor chip, a test system, and a method of testing the semiconductor chip. The semiconductor chip includes a pulse generator configured to generate a test pulse in response to a test request; a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).

Abstract: An equalizer circuit may include an equalizer controller and a plurality of equalizers. The equalizer controller may prove separate sets of enable signals, delay control signals and voltage control signals to the separate equalizers based on a control signal. The equalizers provide equalizer signals to separate connection nodes between separate pairs of logic circuits. An equalizer may be selectively activated based on a received enable signal. An equalizer may include a delay control circuit and a voltage control circuit. The delay control circuit may delay a received transfer signal to generate a delayed transfer signal based on a received delay control signal. The voltage control circuit may generate an equalizer signal based on the delayed transfer signal and a received voltage control signal. The equalizer circuit may reduce inter-symbol interference in the integrated circuit based on providing the equalizer signals to the connection nodes between the logic circuits.

Abstract: A semiconductor memory device and method of operating same are described. The semiconductor memory device includes a first anti-fuse array having a plurality of first anti-fuse elements that store first fuse data, a second anti-fuse array having a plurality of second anti-fuse elements that store error correction code (ECC) data associated with the first fuse data, and an ECC decoder configured to generate second fuse data by correcting the first fuse data using the ECC data.

Abstract: A latency circuit comprises a latency control block, an internal read command generator, and a latency signal generation unit. The latency control block generates a plurality of first control clocks by delaying a delay sync signal generated based on an external clock, and generates a second control clock having a margin with respect to a read command decoded based on the delay sync signal. The internal read command generator samples the second control clock using the decoded read command and generates an internal read command based on a sampled second control clock. The latency signal generation unit generates a latency signal based on a shifting operation performed on the internal read command using the plurality of first control clocks.

Abstract: A semiconductor memory device and method of operating same are described. The semiconductor memory device includes a first anti-fuse array having a plurality of first anti-fuse elements that store first fuse data, a second anti-fuse array having a plurality of second anti-fuse elements that store error correction code (ECC) data associated with the first fuse data, and an ECC decoder configured to generate second fuse data by correcting the first fuse data using the ECC data.