Abstract: There is provided a column repair technology of a semiconductor memory device. The semiconductor memory device includes: a normal bus connection part for transmitting/receiving data between global data buses and local data buses of each bank; a redundant bus connection part for transmitting/receiving data between global data buses and local data buses of each bank; a fuse set having a physical position information of a fail column; and a switching part for selectively connecting outputs of the normal bus connection part and the redundant bus connection part to the global data buses, which corresponds to the fail column, in response to the physical position information of the fail column. The column redundancy scheme can be applied to semiconductor memory devices having such a structure that a lot of column selection lines are enabled with respect to one column address and can also be applied to a case when a fail column address is not present.

Abstract: An apparatus and method for controlling louver blades of a compressor/condenser unit are provided which can improve efficiency of the compressor/condenser unit based on a position of the louver blades and peripheral conditions. The apparatus includes louver blades with a pair of connecting protrusions formed at each end thereof, and a plurality of levers which are rotatably coupled to the connecting protrusions of the louver blades formed in the same positions. A driving member opens and closes the louver blades by moving the levers, and in turn, the louver blades coupled there to. A microcomputer controls the driving member, and the louver blades are opened and closed based on a control signal from the microcomputer.

Abstract: There is provided a column repair technology of a semiconductor memory device. The semiconductor memory device includes: a normal bus connection part for transmitting/receiving data between global data buses and local data buses of each bank; a redundant bus connection part for transmitting/receiving data between global data buses and local data buses of each bank; a fuse set having a physical position information of a fail column; and a switching part for selectively connecting outputs of the normal bus connection part and the redundant bus connection part to the global data buses, which corresponds to the fail column, in response to the physical position information of the fail column. The column redundancy scheme can be applied to semiconductor memory devices having such a structure that a lot of column selection lines are enabled with respect to one column address and can also be applied to a case when a fail column address is not present.