Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a logic cell on a substrate, and a first metal layer on the logic cell. The first metal layer includes first and second power lines and first to third lower lines on first to third wiring tracks therebetween. The first to third wiring tracks extend in parallel in the first direction. The first lower line includes first and second lines spaced apart in the first direction from each other at a first distance. The third lower line includes third and fourth lines spaced apart in the first direction at a second distance. The first line has a first end facing the second line. The third line has a second end facing the fourth line. A curvature at the first end is substantially the same as that at the second end.

Abstract: A method includes grouping, in a first layout, pattern regions which have duplicate layout patterns including weak regions as a group, calculating defect probabilities of the pattern regions, respectively, calculating a defect frequency and a defect rate of the group based on the defect probabilities of the pattern regions, predicting a degree of defects of a second layout of the pattern regions, based on the defect frequency and the defect rate, and performing an extreme ultraviolet (EUV) lithography process on a substrate, based on the second layout. The defect probabilities are calculated by performing an optical proximity correction (OPC) simulation on the pattern region, calculating a stochastic variation of a linewidth of a simulation pattern in the weak region as a Gaussian distribution, and defining a threshold linewidth, which is used as a reference of the random defect, in the Gaussian distribution.

Abstract: An optical proximity correction (OPC) method may include providing a design layout including conductive patterns, determining line end void (LEV)-risk patterns among the conductive patterns, the LEV-risk patterns each having a risk of suffering from poor contact due to an LEV, setting markers including portions of the LEV-risk patterns and portions of the conductive patterns adjacent to the LEV-risk patterns, performing a first OPC on first patterns included in the markers and performing a second OPC on second patterns outside the markers, the second OPC being different from the first OPC, and each of the first OPC and the second OPC being performed a plurality of times, and calculating a cost function of each of the markers. The determining may include comparing risks of occurrence of poor contact in each of the conductive patterns based on a scoring function, and the scoring function may be inversely proportional to a width of each of the conductive patterns.

Abstract: An optical proximity correction (OPC) method may include providing a design layout including conductive patterns, determining line end void (LEV)-risk patterns among the conductive patterns, the LEV-risk patterns each having a risk of suffering from poor contact due to an LEV, setting markers including portions of the LEV-risk patterns and portions of the conductive patterns adjacent to the LEV-risk patterns, performing a first OPC on first patterns included in the markers and performing a second OPC on second patterns outside the markers, the second OPC being different from the first OPC, and each of the first OPC and the second OPC being performed a plurality of times, and calculating a cost function of each of the markers. The determining may include comparing risks of occurrence of poor contact in each of the conductive patterns based on a scoring function, and the scoring function may be inversely proportional to a width of each of the conductive patterns.

Abstract: A lithography metrology method is provided. Focus sensitivity data and dose sensitivity data of sample patterns to be formed on a substrate are acquired. At least one focus pattern selected in descending order of focus sensitivity from among the acquired focus sensitivity data of the sample patterns is determined. At least one low-sensitivity focus pattern in ascending order of the focus sensitivity from among the acquired dose sensitivity data of the sample patterns is selected, and at least one dose pattern selected in descending order of dose sensitivity from among the at least one low-sensitivity focus pattern is determined. A split substrate having a plurality of chip regions is prepared. A plurality of focus split patterns having a shape corresponding to the at least one focus pattern and a plurality of dose split patterns having a shape corresponding to the at least one dose pattern in the plurality of chip regions are formed.

Abstract: A lithography metrology method is provided. Focus sensitivity data and dose sensitivity data of sample patterns to be formed on a substrate are acquired. At least one focus pattern selected in descending order of focus sensitivity from among the acquired focus sensitivity data of the sample patterns is determined. At least one low-sensitivity focus pattern in ascending order of the focus sensitivity from among the acquired dose sensitivity data of the sample patterns is selected, and at least one dose pattern selected in descending order of dose sensitivity from among the at least one low-sensitivity focus pattern is determined. A split substrate having a plurality of chip regions is prepared. A plurality of focus split patterns having a shape corresponding to the at least one focus pattern and a plurality of dose split patterns having a shape corresponding to the at least one dose pattern in the plurality of chip regions are formed.