Abstract: A timing control circuit in an integrated circuit memory device. The circuit has an input line, a first output line and a second output line. The input line configured to receive a control signal for the timing control circuit to generate, a first selection input on the first output line and a second selection input on the second output line. In response to the control signal transitioning from a first state to a second state, the first selection input completes a first transition before the second selection input starts a second transition (e.g., for selection between 0V and ?4.5V); and in response to the control signal transitioning from the second state to the first state, the second selection input completes a third transition before the first selection input starts fourth transition (e.g., for selection between 5V and 1.2V). The sequential transitions avoid simultaneous selection of 5V and ?4.5V.

Abstract: A timing control circuit in an integrated circuit memory device. The circuit has an input line, a first output line and a second output line. The input line configured to receive a control signal for the timing control circuit to generate, a first selection input on the first output line and a second selection input on the second output line. In response to the control signal transitioning from a first state to a second state, the first selection input completes a first transition before the second selection input starts a second transition (e.g., for selection between 0V and ?4.5V); and in response to the control signal transitioning from the second state to the first state, the second selection input completes a third transition before the first selection input starts fourth transition (e.g., for selection between 5V and 1.2V). The sequential transitions avoid simultaneous selection of 5V and ?4.5V.

Abstract: A timing control circuit in an integrated circuit memory device. The circuit has an input line, a first output line and a second output line. The input line configured to receive a control signal for the timing control circuit to generate, a first selection input on the first output line and a second selection input on the second output line. In response to the control signal transitioning from a first state to a second state, the first selection input completes a first transition before the second selection input starts a second transition (e.g., for selection between 0V and ?4.5V); and in response to the control signal transitioning from the second state to the first state, the second selection input completes a third transition before the first selection input starts fourth transition (e.g., for selection between 5V and 1.2V). The sequential transitions avoid simultaneous selection of 5V and ?4.5V.

Abstract: A semiconductor memory device having first and second memory architectures with different structures and allowing the possibility of selecting any one of the first and second memory architectures using a selection process and a memory system using the semiconductor memory device are provided. The first memory architecture has p banks, a page size of m/2 bytes of m/2 memory cells connected to one word line in each of the banks, and n/2 data terminals DQ. The second memory architecture has p banks, a page size of m bytes, and n data terminals. The option process may be realized by a bonding, a mask pattern, or a fuse. In a memory device, the page size and the number of memory banks are adjusted by a design option. Thus, the memory architecture is modified, redundancy flexibility is increased and power consumption is reduced.

Abstract: A semiconductor memory device internal voltage generator and internal voltage generating method are disclosed. The device and method are capable of supplying a uniform amount of electric charge and generating a stable internal voltage, despite variations in an external voltage. The internal voltage generator includes a PMOS driving transistor having a source connected to the external voltage, a gate connected to a driving signal, and a drain that supplies the internal voltage. The interval voltage generator also includes a driving signal generator that generates the driving signal in response to a control signal. The driving signal generator maintains a voltage between the gate and source of the PMOS driving transistor at a substantially uniform voltage level despite variations in the external voltage.

Abstract: A semiconductor memory device having first and second memory architectures with different structures and allowing the possibility of selecting any one of the first and second memory architectures using a selection process and a memory system using the semiconductor memory device are provided. The first memory architecture has p banks, a page size of m/2 bytes of m/2 memory cells connected to one word line in each of the banks, and n/2 data terminals DQ. The second memory architecture has p banks, a page size of m bytes, and n data terminals. The option process may be realized by a bonding, a mask pattern, or a fuse. In a memory device, the page size and the number of memory banks are adjusted by a design option. Thus, the memory architecture is modified, redundancy flexibility is increased and power consumption is reduced.

Abstract: A semiconductor memory device internal voltage generator and internal voltage generating method are disclosed. The device and method are capable of supplying a uniform amount of electric charge and generating a stable internal voltage, despite variations in an external voltage. The internal voltage generator includes a PMOS driving transistor having a source connected to the external voltage, a gate connected to a driving signal, and a drain that supplies the internal voltage. The interval voltage generator also includes a driving signal generator that generates the driving signal in response to a control signal. The driving signal generator maintains a voltage between the gate and source of the PMOS driving transistor at a substantially uniform voltage level despite variations in the external voltage.

Abstract: A semiconductor memory device having a column redundancy scheme for improving redundancy efficiency includes sub memory blocks, a redundancy memory block, global data input output lines respectively associated with the sub memory blocks, a redundancy global data input output line and switches. Each of the sub memory blocks has a plurality of memory cells. The redundancy memory block has a plurality of redundancy memory cells. The data of selected memory cells of a sub memory block are transmitted to a corresponding global data input output line. The data of selected redundancy memory cells of the redundancy memory block are transmitted to the redundancy global data input output line. A switch switches the global data input output line to the redundancy global data input output line if a memory cell connected to the global data input output line is defective.

Abstract: Reference voltage regulators and methods for integrated circuit output driver systems generate an initial supplementary current for the integrated circuit output driver system at the reference voltage for a predetermined time period in response to an output enable signal. Preferably, sufficient initial supplementary current is generated to compensate for an initial drop in the reference voltage that is generated by a reference voltage generator upon initial activation of the output driver system. Reference voltage generators according to embodiments of the invention may be included in an integrated circuit output driver system that is responsive to a reference voltage and to an output enable signal, and that varies in current drive capability in response to a current drive control signal. These embodiments of reference voltage regulators include a reference voltage generator that generates the reference voltage for the integrated circuit output driver system.

Abstract: A semiconductor memory device having a column redundancy scheme for improving redundancy efficiency includes sub memory blocks, a redundancy memory block, global data input output lines respectively associated with the sub memory blocks, a redundancy global data input output line and switches. Each of the sub memory blocks has a plurality of memory cells. The redundancy memory block has a plurality of redundancy memory cells. The data of selected memory cells of a sub memory block are transmitted to a corresponding global data input output line. The data of selected redundancy memory cells of the redundancy memory block are transmitted to the redundancy global data input output line. A switch switches the global data input output line to the redundancy global data input output line if a memory cell connected to the global data input output line is defective.

Abstract: A highly effective charge pump circuit includes a pulse generator for generating a pulse signal in response to a control signal, a first voltage pumping unit for generating a first high voltage in response to the control signal and the pulse signal, a second voltage pumping unit for generating a second high voltage of the same level as the first high voltage in response to the control signal and the pulse signal, and a voltage transmitting unit that receives and outputs first high voltage when the second high voltage is applied. The charge pump obtains a high voltage using NMOS transistors.

Abstract: High speed address decoders may include a predecoder and a main decoder that are both responsive to a control signal. The predecoder switches from an active state to an inactive state in response to a transition of the control signal from a first logic state to a second logic state. Conversely, the main decoder commences switching from an inactive state to an active state simultaneously with the transition of the control signal from the first logic state to the second logic state. The predecoder may generate a predecoded address signal while the control signal is in the first logic state, which may then be decoded by the main decoder to activate a line enable signal when the control signal transitions to the second logic state. As a result, address decoding speed may be improved thereby facilitating higher speed operation of an integrated circuit memory device.

Abstract: An integrated circuit device is provided having a column selection circuit which activates the column selection line output responsive to a column latch signal rather than a data command signal. The leading edge of the column latch signal is used to generate a master clock signal and to latch the selected address. The master clock signal is delayed and a column decoder circuit decodes the latched selected address to activate the appropriate column selection line output responsive to the delayed clock. As activation of the column selection line output initiates placement of the desired sense amplified bit line signal on the local input and output lines, the voltage differential on the local input and output lines can begin to develop earlier than with the prior art approaches.

Abstract: An integrated circuit memory device and method including a direct mode assigns internal data and address signals to separate pins. In particular, a plurality of first pins is assigned to the plurality of internal data signals that provide the data to the memory array in direct test mode. A plurality of second pins is assigned to the plurality of internal address signals that provide the address to the memory array in direct test mode, wherein none of the pins included in first plurality of pins are included in the second plurality of pins.