Patents by Inventor Byung-sik Moon
Byung-sik Moon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9245827Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.Type: GrantFiled: April 25, 2014Date of Patent: January 26, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Uk-song Kang, Dong-hyeon Jang, Seong-jin Jang, Hoon Lee, Jin-ho Kim, Nam-seog Kim, Byung-sik Moon, Woo-dong Lee
-
Patent number: 8848475Abstract: A fuse circuit includes a program unit and a sensing unit. The program unit is programmed in response to a program signal and outputs a program output signal in response to a sensing enable signal. The sensing unit outputs a sensing output signal based on the program output signal and the sensing output signal indicates whether the program unit is programmed or not. The program unit includes an anti-fuse cell, a selection transistor, a program transistor and a sensing transistor. The anti-fuse cell includes at least two anti-fuse elements which are connected in parallel and are respectively broken down at different levels of a program voltage.Type: GrantFiled: August 29, 2011Date of Patent: September 30, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Pil Son, Seong-Jin Jang, Byung-Sik Moon, Hyuck-Chai Jung, Ju-Seop Park
-
Publication number: 20140233292Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.Type: ApplicationFiled: April 25, 2014Publication date: August 21, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Uk-song Kang, Dong-hyeon Jang, Seong-jin Jang, Hoon Lee, Jin-ho Kim, Nam-seog Kim, Byung-sik Moon, Woo-dong Lee
-
Patent number: 8743582Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.Type: GrantFiled: May 25, 2011Date of Patent: June 3, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Uk-song Kang, Dong-hyeon Jang, Seong-jin Jang, Hoon Lee, Jin-ho Kim, Nam-seog Kim, Byung-sik Moon, Woo-dong Lee
-
Patent number: 8599635Abstract: A fuse circuit includes a program unit, a sensing unit and a control unit. The program unit is programmed in response to a program signal, and outputs a program output signal in response to a sensing enable signal. The sensing unit includes a variable resistor unit that has a resistance that varies based on a control signal, and generates a sensing output signal based on the resistance of the variable resistor unit and the program output signal. The control unit generates the control signal having a value changed depending on operation modes, and performs a verification operation with respect to the program unit based on the sensing output signal to generate a verification result. The program unit may be re-programmed based on the verification result.Type: GrantFiled: August 9, 2011Date of Patent: December 3, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Ho Kim, Jong-Pil Son, Seong-Jin Jang, Byung-Sik Moon, Seung-Hoon Oh, Ju-Seop Park
-
Patent number: 8547763Abstract: A memory cell includes a selection transistor on a substrate and an antifuse on the substrate. The selection transistor includes a first gate connected to a read word line, a first gate insulation layer that insulates the first gate from the substrate, a first source region connected to a bit line, and a first drain region, an impurity concentration of the first drain region being lower than an impurity concentration of the first source region. The antifuse includes a first electrode connected to a program word line and a second electrode connected to the selection transistor.Type: GrantFiled: August 29, 2011Date of Patent: October 1, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Pil Son, Seong-Jin Jang, Byung-Sik Moon, Doo-Young Kim, Ju-Seop Park
-
Patent number: 8514648Abstract: Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate.Type: GrantFiled: March 18, 2011Date of Patent: August 20, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Pil Son, Seong-Jin Jang, Byung-Sik Moon, Doo-Young Kim, Hyoung-Joo Kim, Ju-Seop Park
-
Patent number: 8495437Abstract: A semiconductor memory device including a data bus inversion (DBI) determination unit, a first inverter, a cyclic redundancy check (CRC) calculation unit, a second inverter, and a DQ pin. The DBI determination unit is configured to determine whether to perform DBI based on first data on a main data line and configured to generate DBI data. The first inverter is configured to invert or non-invert the first data according to the DBI data to generate second data. The CRC calculation unit is configured to generate CRC data based on the second data and the DBI data. The second inverter is configured to invert or non-invert the first data according to the DBI data to generate third data. The DQ pin is configured to output the third data externally.Type: GrantFiled: September 4, 2012Date of Patent: July 23, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Kyo-min Sohn, Byung-sik Moon
-
Patent number: 8482989Abstract: Provided are a semiconductor device including a fuse and a method of operating the same. The semiconductor device includes a fuse array, a first register unit, and a second register unit. The fuse array includes a plurality of rows and columns. The first register unit receives at least one row of fuse data from the fuse array. Fuse data of the at least one row of fuse data is received in parallel by the first register unit. The second register unit receives the fuse data at least one bit at a time from the first register unit.Type: GrantFiled: November 14, 2011Date of Patent: July 9, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-pil Son, Seong-jin Jang, Byung-sik Moon, Ju-seop Park
-
Publication number: 20130061102Abstract: A semiconductor memory device including a data bus inversion (DBI) determination unit, a first inverter, a cyclic redundancy check (CRC) calculation unit, a second inverter, and a DQ pin. The DBI determination unit is configured to determine whether to perform DBI based on first data on a main data line and configured to generate DBI data. The first inverter is configured to invert or non-invert the first data according to the DBI data to generate second data. The CRC calculation unit is configured to generate CRC data based on the second data and the DBI data. The second inverter is configured to invert or non-invert the first data according to the DBI data to generate third data. The DQ pin is configured to output the third data externally.Type: ApplicationFiled: September 4, 2012Publication date: March 7, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyo-min SOHN, Byung-sik MOON
-
Publication number: 20130003477Abstract: A semiconductor memory device including an antifuse cell array and a spare antifuse cell array are provided. An antifuse cell array includes a first set of antifuse cells arranged in a first direction and each one of the first set of antifuse cells is connected to a corresponding one of first through nth word lines. The spare antifuse cell array includes a first spare set of antifuse cells arranged in the first direction and each one of the first spare set of antifuse cells is connected to a corresponding one of first through kth spare word lines. A first operation control circuit is configured to program antifuses of the antifuse cell array and the spare antifuse cell array, and to read a status of each of the antifuses. The first operation control circuit is commonly connected to the first set of antifuse cells and the first spare set of antifuse cells.Type: ApplicationFiled: June 27, 2012Publication date: January 3, 2013Inventors: Ju-Seop PARK, Sin Ho KIM, Byung-Sik MOON, Jong-Pil SON, Jin-Ho KIM, Hyoung-Joo KIM, Jong-Min OH, Seong-Jin JANG
-
Publication number: 20120120733Abstract: Provided are a semiconductor device including a fuse and a method of operating the same. The semiconductor device includes a fuse array, a first register unit, and a second register unit. The fuse array includes a plurality of rows and columns. The first register unit receives at least one row of fuse data from the fuse array. Fuse data of the at least one row of fuse data is received in parallel by the first register unit. The second register unit receives the fuse data at least one bit at a time from the first register unit.Type: ApplicationFiled: November 14, 2011Publication date: May 17, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-pil Son, Seong-jin Jang, Byung-sik Moon, Ju-seop Park
-
Publication number: 20120051154Abstract: A fuse circuit includes a program unit and a sensing unit. The program unit is programmed in response to a program signal and outputs a program output signal in response to a sensing enable signal. The sensing unit outputs a sensing output signal based on the program output signal and the sensing output signal indicates whether the program unit is programmed or not. The program unit includes an anti-fuse cell, a selection transistor, a program transistor and a sensing transistor. The anti-fuse cell includes at least two anti-fuse elements which are connected in parallel and are respectively broken down at different levels of a program voltage.Type: ApplicationFiled: August 29, 2011Publication date: March 1, 2012Applicant: Samsung Electronics Co., Ltd.Inventors: Jong-Pil SON, Seong-Jin Jang, Byung-Sik Moon, Hyuck-Chai Jung, Ju-Seop Park
-
Publication number: 20120051164Abstract: A memory cell includes a selection transistor on a substrate and an antifuse on the substrate. The selection transistor includes a first gate connected to a read word line, a first gate insulation layer that insulates the first gate from the substrate, a first source region connected to a bit line, and a first drain region, an impurity concentration of the first drain region being lower than an impurity concentration of the first source region. The antifuse includes a first electrode connected to a program word line and a second electrode connected to the selection transistor.Type: ApplicationFiled: August 29, 2011Publication date: March 1, 2012Inventors: Jong-Pil Son, Seong-Jin Jang, Byung-Sik Moon, Doo-Young Kim, Ju-Seop Park
-
Publication number: 20120039140Abstract: A fuse circuit includes a program unit, a sensing unit and a control unit. The program unit is programmed in response to a program signal, and outputs a program output signal in response to a sensing enable signal. The sensing unit includes a variable resistor unit that has a resistance that varies based on a control signal, and generates a sensing output signal based on the resistance of the variable resistor unit and the program output signal. The control unit generates the control signal having a value changed depending on operation modes, and performs a verification operation with respect to the program unit based on the sensing output signal to generate a verification result. The program unit may be re-programmed based on the verification result.Type: ApplicationFiled: August 9, 2011Publication date: February 16, 2012Inventors: Jin-Ho KIM, Jong-Pil SON, Seong-Jin JANG, Byung-Sik MOON, Seung-Hoon OH, Ju-Seop PARK
-
Publication number: 20110292708Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.Type: ApplicationFiled: May 25, 2011Publication date: December 1, 2011Inventors: Uk-song Kang, Dong-hyeon Jang, Seong-jin Jang, Hoon Lee, Jin-ho Kim, Nam-seog Kim, Byung-sik Moon, Woo-dong Lee
-
Publication number: 20110267915Abstract: Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate.Type: ApplicationFiled: March 18, 2011Publication date: November 3, 2011Inventors: Jong-Pil SON, Seong-Jin Jang, Byung-Sik Moon, Doo-Young Kim, Hyoung-Joo Kim, Ju-Seop Park
-
Patent number: 8045404Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cells coupled between a plurality of word lines and a plurality of bit line pairs, a bit line selection circuit configured to transmit data between a selected bit line pair and a local input/output line pair in response to a column selection signal, a local global input/output gate circuit configured to transmit data between the local input/output line pair and a global input/output line pair in response to a local global input/output selection signal, and a controller configured to drive the word lines, output the column selection signal having a first voltage level to the bit line selection circuit, and output the local global input/output selection signal having a second voltage level that is lower than the first voltage level to the local global input/output gate circuit, in response to an external address signal and an external command.Type: GrantFiled: February 26, 2010Date of Patent: October 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Hyun Lee, Byung-Sik Moon, Seung-Bum Ko
-
Patent number: 7898881Abstract: A semiconductor memory device includes first and second edge drivers configured to generate sensing control signals, a memory cell array between first and second edge drivers, and pluralities of unit sense amplifiers detecting data from the memory cell array in response to the sensing control signals.Type: GrantFiled: July 23, 2008Date of Patent: March 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hwa Choi, Byung-Sik Moon
-
Publication number: 20100226187Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cells coupled between a plurality of word lines and a plurality of bit line pairs, a bit line selection circuit configured to transmit data between a selected bit line pair and a local input/output line pair in response to a column selection signal, a local global input/output gate circuit configured to transmit data between the local input/output line pair and a global input/output line pair in response to a local global input/output selection signal, and a controller configured to drive the word lines, output the column selection signal having a first voltage level to the bit line selection circuit, and output the local global input/output selection signal having a second voltage level that is lower than the first voltage level to the local global input/output gate circuit, in response to an external address signal and an external command.Type: ApplicationFiled: February 26, 2010Publication date: September 9, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Byung-Hyun Lee, Byung-Sik Moon, Seung-Bum Ko