Patents by Inventor Byung-Su Koo

Byung-Su Koo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6472269
    Abstract: The present invention relates to a method for fabricating a capacitor of a semiconductor device to prevent an occurrence of an operational failure of a capacitor caused by the cleaning steps that follow the process of doping PH3 into an HSG. This improves the quality of the fabricated capacitor and simplifies the operational processes of manufacture. The method includes the steps of forming an insulating interlayer over a semiconductor substrate, forming a buried contact hole in the insulating interlayer to expose a predetermined portion of the semiconductor substrate, forming a lower electrode over the insulating interlayer and in the buried contact hole, performing a first cleaning process, growing an HSG on an exposed portion of the lower electrode, performing a second cleaning process, doping PH3 into the HSG, and forming a dielectric layer over the HSG and the lower electrode.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: October 29, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Woo Kwak, Jung-Hun Yun, Byung-Su Koo, Su-Young Kwon
  • Publication number: 20020102792
    Abstract: The present invention relates to a method for fabricating a capacitor of a semiconductor device to prevent an occurrence of an operational failure of a capacitor caused by the cleaning steps that follow the process of doping PH3 into an HSG. This improves the quality of the fabricated capacitor and simplifies the operational processes of manufacture. The method includes the steps of forming an insulating interlayer over a semiconductor substrate, forming a buried contact hole in the insulating interlayer to expose a predetermined portion of the semiconductor substrate, forming a lower electrode over the insulating interlayer and in the buried contact hole, performing a first cleaning process, growing an HSG on an exposed portion of the lower electrode, performing a second cleaning process, doping PH3 into the HSG, and forming a dielectric layer over the HSG and the lower electrode.
    Type: Application
    Filed: March 14, 2002
    Publication date: August 1, 2002
    Inventors: Sun-Woo Kwak, Jung-Hun Yun, Byung-Su Koo, Su-Young Kwon
  • Patent number: 6391715
    Abstract: The present invention relates to a method for fabricating a capacitor of a semiconductor device to prevent an occurrence of an operational failure of a capacitor caused by the cleaning steps that follow the process of doping PH3 into an HSG. This improves the quality of the fabricated capacitor and simplifies the operational processes of manufacture. The method includes the steps of forming an insulating interlayer over a semiconductor substrate, forming a buried contact hole in the insulating interlayer to expose a predetermined portion of the semiconductor substrate, forming a lower electrode over the insulating interlayer and in the buried contact hole, performing a first cleaning process, growing an HSG on an exposed portion of the lower electrode, performing a second cleaning process, doping PH3 into the HSG, and forming a dielectric layer over the HSG and the lower electrode.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: May 21, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Woo Kwak, Jung-Hun Yun, Byung-Su Koo, Su-Young Kwon
  • Patent number: 6265261
    Abstract: A method of fabricating a semiconductor device includes nitriding a native oxide layer on a pattern of polysilicon layers to be used as the lower electrode of a capacitor in LPCVD equipment at a constant temperature in an environment of ammonia gas. A nitride layer is then deposited onto the nitrided native oxide layer in the in-situ state. An oxide layer is then deposited onto the entire nitride layer, and thereafter a pattern of upper electrodes are formed on the oxide layer, thereby shortening the period of time required for forming the entire nitride layer of the NO dielectric layer without any deterioration in the product quality.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: July 24, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Young Kim, Kyoung-Ho Hyon, Joong-Il An, Byung-Su Koo
  • Patent number: 6265264
    Abstract: A method of fabricating a capacitor of a semiconductor device maximizes the imurity density of HSG formed at a surface of an electrode of the capacitor and thereby improves capacitance and breakdown voltage characteristics of a DRAM device incorporating the same. The method includes forming an inter-level insulating layer having a buried contact hole which exposes the underlying semiconductor substrate, forming an amorphous polysilicon layer doped with a low density of a p-type impurity on the resultant structure, selectively etching the polysilicon layer with a mask having a pattern configured to form a bottom electrode over a predetermined portion of the inter-level insulating layer which includes the contact hole, causing HSG to grow on the exposed surface of the bottom electrode, and doping PH3 into the HSG under a “low temperature/ high pressure” process condition.
    Type: Grant
    Filed: April 12, 2000
    Date of Patent: July 24, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joong-Il An, Kyung-Ho Hyun, Byung-Su Koo, Sun-Woo Kwak