Abstract: An electronic circuitry is provided for reading out a memory element (ME). The electronic circuitry comprises a first electronic path (IP) being coupled to the memory element (ME), a second electronic path (RP) having predetermined electrical properties, and a basic detection element (BDE) being coupled to the first and second electronic paths (IP, RP) such that the information contained in the memory element (ME) can be determined by the basic detection element (BDE) based on the relation of a digital signal being propagated over the first path (IP) to a digital signal being propagated over the second path (RP).

Abstract: The present invention relates to a monitor cell (200) for monitoring local variations in a process parameter of an integrated circuit. The monitor cell (200) comprises a first delay path (220) located in a first area (100, 110, 120) of the integrated circuit and a second delay path (230) located in a second area (100, 110, 120) of the integrated circuit. The first delay path (220) is faster than the second delay path (230) when the difference in the respective process parameter values of the first area and the second area is smaller than a predefined threshold. In contrast, the second delay path (230) is faster than the first delay path (220) when said difference is larger than the predefined threshold. The monitor cell further comprises an input (210) arranged to provide the first delay path (220) and the second delay path (230) with a test signal (260) and a signal detector (240) for detecting the order in which the delay paths (210; 220) output the test signal (260).

Abstract: A SRAM memory cell including two inverters and a plurality of switches is provided. The SRAM cell is manufactured in a technology offering N/P shunt capabilities and the inputs of the inverters are connected to at least one pair of bit lines (BLa, BLa/; BLb, BLb/) via two of the switches. The switches are controlled by a signal word line (WLa, WLb). Each inverter includes a first transistor (MN0, MN1) of a first conductivity type and a second transistor (MP0, MP1) of a second conductivity type. Each switch includes at least a third transistor (MN2, MN3) of the first conductivity type, characterized in that the two transistors (MP0, MP1) of the second conductivity type in the inverters are arranged in two opposite end regions of the memory cell, respectively.

Abstract: An electronic circuitry is provided for reading out a memory element (ME). The electronic circuitry comprises a first electronic path (IP) being coupled to the memory element (ME), a second electronic path (RP) having predetermined electrical properties, and a basic detection element (BDE) being coupled to the first and second electronic paths (IP, RP) such that the information contained in the memory element (ME) can be determined by the basic detection element (BDE) based on the relation of a digital signal being propagated over the first path (IP) to a digital signal being propagated over the second path (RP).

Abstract: The invention proposes a SRAM memory cell comprising two inverters and, a plurality of switches, the SRAM cell being manufactured in a technology offering N/P shunt capabilities, the inputs of the inverters being connected to at least one pair of bit lines (BLa, BLa/; BLb, BLb/) via two of said switches, said switches being controlled by a signal word line (WLa, WLb), each inverter comprising a first transistor (MN0, MN1) of a first conductivity type and a second transistor (MP0, MP1) of a second conductivity type, and each switch comprising at least a third transistor (MN2, MN3) of the first conductivity type, characterized in that the two transistors (MP0, MP1) of the second conductivity type in the inverters are arranged in two opposite end regions of the memory cell, respectively.

Abstract: A SRAM on an SOI substrate comprising a network of rows and columns of 6T memory cells with two inverters and two switch transistors, each cell being connected to two bit lines and to one of the word lines. Each memory cell comprises two first regions of the first conductivity type, each first region comprising the drains or the sources of first and third transistors, and being in contact with a second region of the second conductivity type comprising the drain or the source of a second transistor, the first and second regions being short-circuited by a conductive material, the conductive tracks of the first level taking part in the interconnections between the inverters, and in the interconnections between the switch transistors and the word line being parallel to the bit lines.

Abstract: A SRAM on an SOI substrate comprising a network of rows and columns of 6T memory cells with two inverters and two switch transistors, each cell being connected to two bit lines and to one of the word lines. Each memory cell comprises two first regions of the first conductivity type, each first region comprising the drains or the sources of first and third transistors, and being in contact with a second region of the second conductivity type comprising the drain or the source of a second transistor, the first and second regions being short-circuited by a conductive material, the conductive tracks of the first level taking part in the interconnections between the inverters, and in the interconnections between the switch transistors and the word line being parallel to the bit lines.