Abstract: Provided are transistor devices such as logic gates that are capable of associating a computational state and or performing logic operations with detectable electronic spin state and or magnetic state. Methods of operating transistor devices employing magnetic states are provided. Devices comprise input and output structures and magnetic films capable of being converted between magnetic states.

Abstract: Provided are transistor devices such as logic gates that are capable of associating a computational state and or performing logic operations with detectable electronic spin state and or magnetic state. Methods of operating transistor devices employing magnetic states are provided. Devices comprise input and output structures and magnetic films capable of being converted between magnetic states.

Abstract: A nano-sized metal particle composition includes a first metal that has a particle size of about 20 nanometer or smaller. The nano-sized metal particle can include a second metal that forms a shell about the first metal. A microelectronic package is also disclosed that uses the nano-sized metal particle composition. A method of assembling a microelectronic package is also disclosed. A computing system is also disclosed that includes the nano-sized metal particle composition.

Abstract: Apparatus and system, as well as fabrication methods therefor, may include a thermal intermediate structure comprised of a plurality of carbon nanotubes some of which have organic moieties attached thereto to tether the nanotubes to at least one of a die and a heat sink. The organic moieties include thiol linkers and amide linkers.

Abstract: Apparatus and system, as well as fabrication methods therefor, may include a thermal intermediate structure comprised of a plurality of carbon nanotubes some of which have organic moieties attached thereto to tether the nanotubes to at least one of a die and a heat sink. The organic moieties include thiol linkers and amide linkers.

Abstract: An apparatus and system, may include a thermal interface material comprised of an array of carbon nanotubes and a buffer layer disposed between the thermal interface material and one of a die or a heat spreader. In some embodiments the carbon nanotubes may be formed above a buffer layer formed above a surface of the heat spreader.

Abstract: A composite carbon nanotube structure including a number of carbon nanotubes disposed in a metal matrix. The composite carbon nanotube structure may be used as a thermal interface device in a packaged integrated circuit device.

Abstract: The various embodiments of coaxial capacitors are self-aligned and formed in a via, including blind vias, buried vias and plated through holes. The coaxial capacitors are adapted to utilize the plating of a plated via as a first electrode. The dielectric layer is formed to overlie the first electrode while leaving a portion of the via unfilled. A second electrode is formed in the portion of the via left unfilled by the dielectric layer. Such coaxial capacitors are suited for use in decoupling and power dampening applications to reduce signal and power noise and/or reduce power overshoot and droop in electronic devices. For such applications, it is generally expected that a plurality of coaxial capacitors, often numbering in the thousands, will be coupled in parallel in order to achieve the desired level of capacitance.

Abstract: An apparatus and system, as well as fabrication methods therefor, may include a thermal interface material comprised of an array of carbon nanotubes and a buffer layer disposed between the thermal interface material and one of a die or a heat spreader.

Abstract: A composite carbon nanotube structure comprising a number of carbon nanotubes disposed in a metal matrix. The composite carbon nanotube structure may be used as a thermal interface device in a packaged integrated circuit device.

Abstract: Processes are described whereby a wafer is manufactured, a die from the wafer, and an electronic assembly including the die. The die has a diamond layer which primarily serves to spread heat from hot spots of an integrated circuit in the die.

Abstract: The various embodiments of coaxial capacitors are self-aligned and formed in a via, including blind vias, buried vias and plated through holes. The coaxial capacitors are adapted to utilize the plating of a plated via as a first electrode. The dielectric layer is formed to overlie the first electrode while leaving a portion of the via unfilled. A second electrode is formed in the portion of the via left unfilled by the dielectric layer. Such coaxial capacitors are suited for use in decoupling and power dampening applications to reduce signal and power noise and/or reduce power overshoot and droop in electronic devices. For such applications, it is generally expected that a plurality of coaxial capacitors, often numbering in the thousands, will be coupled in parallel in order to achieve the desired level of capacitance.

Abstract: The various embodiments of coaxial capacitors are self-aligned and formed in a via, including blind vias, buried vias and plated through holes. The coaxial capacitors are adapted to utilize the plating of a plated via as a first electrode. The dielectric layer is formed to overlie the first electrode while leaving a portion of the via unfilled. A second electrode is formed in the portion of the via left unfilled by the dielectric layer. Such coaxial capacitors are suited for use in decoupling and power dampening applications to reduce signal and power noise and/or reduce power overshoot and droop in electronic devices. For such applications, it is generally expected that a plurality of coaxial capacitors, often numbering in the thousands, will be coupled in parallel in order to achieve the desired level of capacitance.

Abstract: Processes are described whereby a wafer is manufactured, a die from the wafer, and an electronic assembly including the die. The die has a diamond layer which primarily serves to spread heat from hot spots of an integrated circuit in the die.

Abstract: The various embodiments of coaxial capacitors are self-aligned and formed in a via, including blind vias, buried vias and plated through holes. The coaxial capacitors are adapted to utilize the plating of a plated via as a first electrode. The dielectric layer is formed to overlie the first electrode while leaving a portion of the via unfilled. A second electrode is formed in the portion of the via left unfilled by the dielectric layer. Such coaxial capacitors are suited for use in decoupling and power dampening applications to reduce signal and power noise and/or reduce power overshoot and droop in electronic devices. For such applications, it is generally expected that a plurality of coaxial capacitors, often numbering in the thousands, will be coupled in parallel in order to achieve the desired level of capacitance.