Patents by Inventor C. Neil Berglund

C. Neil Berglund has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6803582
    Abstract: A beam array includes a base plate, a plurality of conductor pads, and a ground plate. The conductor pads are arranged in a one-dimensional array on the base plate. The ground plate is coupled to the base plate over the plurality of conductor pads with a gap between the base plate and the ground plate. Each of the plurality of conductor pads forms a beam blanker across the gap with the ground plate.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: October 12, 2004
    Assignee: Oregon Health & Science University
    Inventor: C. Neil Berglund
  • Publication number: 20040104353
    Abstract: A beam blanker array includes a base plate, a plurality of conductor pads, and a ground plate. The conductor pads are arranged in a one-dimensional array on the base plate. The ground plate is coupled to the base plate over the plurality of conductor pads with a gap between the base plate and the ground plate. Each of the plurality of conductor pads forms a beam blanker across the gap with the ground plate.
    Type: Application
    Filed: May 2, 2003
    Publication date: June 3, 2004
    Inventor: C. Neil Berglund
  • Patent number: 6376985
    Abstract: A photocathode having a gate electrode so that modulation of the resulting electron beam is accomplished independently of the laser beam. The photocathode includes a transparent substrate, a photoemitter, and an electrically separate gate electrode surrounding an emission region of the photoemitter. The electron beam emission from the emission region is modulated by voltages supplied to the gate electrode. In addition, the gate electrode may have multiple segments that are capable of shaping the electron beam in response to voltages supplied individually to each of the multiple segments.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: April 23, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Kim Y. Lee, Tai-Hon Philip Chang, Marian Mankos, C. Neil Berglund
  • Publication number: 20010038263
    Abstract: A photocathode having a gate electrode so that modulation of the resulting electron beam is accomplished independently of the laser beam. The photocathode includes a transparent substrate, a photoemitter, and an electrically separate gate electrode surrounding an emission region of the photoemitter. The electron beam emission from the emission region is modulated by voltages supplied to the gate electrode. In addition, the gate electrode may have multiple segments that are capable of shaping the electron beam in response to voltages supplied individually to each of the multiple segments.
    Type: Application
    Filed: March 31, 1998
    Publication date: November 8, 2001
    Inventors: KIM Y. LEE, TAI-HON PHILIP CHANG, MARIAN MANKOS, C. NEIL BERGLUND
  • Patent number: 6220914
    Abstract: A photocathode having a gate electrode so that modulation of the resulting electron beam is accomplished independently of the laser beam. The photocathode includes a transparent substrate, a photoemitter, and an electrically separate gate electrode surrounding an emission region of the photoemitter. The electron beam emission from the emission region is modulated by voltages supplied to the gate electrode. In addition, the gate electrode may have multiple segments that are capable of shaping the electron beam in response to voltages supplied individually to each of the multiple segments.
    Type: Grant
    Filed: November 24, 1999
    Date of Patent: April 24, 2001
    Assignee: Etec Systems, Inc.
    Inventors: Kim Y. Lee, Tai-Hon Philip Chang, Marian Mankos, C. Neil Berglund
  • Patent number: 6145438
    Abstract: In electron beam lithography, a lithography system uses multiple microcolumns in an array to increase throughput for direct writing of semiconductor wafers. The mismatch between the microcolumn array and the semiconductor die periodicity is resolved by using only one microcolumn to scan each individual die. This is accomplished by assuring that the stage carrying the semiconductor wafer moves a total distance in each of the X and Y directions which is greater than the pitch between adjacent die. Hence each die is scanned by only a single microcolumn although at possibly different times during the total stage motion.
    Type: Grant
    Filed: March 20, 1998
    Date of Patent: November 14, 2000
    Inventors: C. Neil Berglund, Tai-Hon Philip Chang
  • Patent number: 5393987
    Abstract: A raster scan lithography system is modified so that the duration of illumination (dose modulation) for particular pixels is varied to lie between the full on and full off normally used. For instance, three levels of pixel intensity are provided, 100%, 70% and 30% (in addition to off which is 0%). The 30% and 70% pixels are used along the edge of a feature so as to locate the edge when written in between the lines of the cartesian raster scan grid. Thus the edges of the feature are moved off the grid, without the need for multiple passes. This pixel dose modulation uses three preset delay lines determining dwell times for each pixel on a pixel-by-pixel basis, as defined by a two (or more) bit deep memory file associated with the pattern to be written. Additionally, the pixel center locations are directly moved off the grid by deflecting the beam as it scans certain pixels located along feature edges. The amount of deflection is controllably variable to achieve various edge locations.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: February 28, 1995
    Assignee: ETEC Systems, Inc.
    Inventors: Frank E. Abboud, Andrew J. Muray, C. Neil Berglund
  • Patent number: 5103101
    Abstract: A method for a raster scan particle or light beam lithography system for writing in multiple passes interleaved in such a manner as to achieve a composite result nearly identical to normal single pass raster scan writing with overlapped spots. Multiple pass writing, achieved with little or no degradation or throughput or lithography quality, provides an ideal platform for implementation of known image averaging techniques to improve lithography quality. This technique is combined with the known writing technique of "Virtual Addressing" to improve resolution with little or no degradation of throughput.
    Type: Grant
    Filed: March 4, 1991
    Date of Patent: April 7, 1992
    Assignee: Etec Systems, Inc.
    Inventors: C. Neil Berglund, John R. Thomas, John T. Poreda
  • Patent number: 5086477
    Abstract: A system for extracting design information from a semiconductor integrated circuit (IC) is disclosed. The system includes a microscope and camera for capturing a composite image of the IC in the form of a video signal. Image capture occurs on a section-by-section basis in which a "snapshot" of each section is taken, the die-holding table stepped to a new section, and a snapshot of the new section obtained. This image capture operation continues until a composite image of the IC is obtained by successive capture of contiguous or partially overlapping images covering all of the different sections of the die. An image processor receives the video signal from the optical means and generates an abstract representation of the die in the form of lists of identifying features such as the size, type and relative location of all transistors, and the width, length and relative location of all of the metal interconnects to the IC.
    Type: Grant
    Filed: August 7, 1990
    Date of Patent: February 4, 1992
    Assignee: Northwest Technology Corp.
    Inventors: Kenneth K. Yu, C. Neil Berglund
  • Patent number: 4409259
    Abstract: A high density CMOS dynamic RAM cell comprising a transistor and capacitance means formed in an n-well is disclosed. The capacitance means includes a polysilicon plate member disposed above a p-type region formed in the n-well. A buried contact, extending from the plate member, pierces the p-type region and contacts the well. In addition to the capacitance associated with the plate member, p-type region and well, capacitance is obtained between the side walls of the n-type regions and p-type regions.
    Type: Grant
    Filed: July 29, 1982
    Date of Patent: October 11, 1983
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Kenneth K. Yu, Ronald J. C. Chwang, C. Neil Berglund