Abstract: An image sensor includes an array of pixels on a semiconductor device for sensing light incident on the pixel array and a plurality of anomaly registers comprising a plurality of nonvolatile elements. Each anomaly register identifies an anomalous pixel cluster and includes a location indicator with a row and column address and a size indicator with a horizontal and vertical range. In other embodiments, each anomaly register includes a first address, second address, first direction flag, and second direction flag. The first and second direction flags use a first state to indicate a row address or a second state to indicate a column address. The first and second direction flags combine to define an anomalous pixel cluster, a pair of anomalous pixel rows, or a pair of anomalous pixel columns. Some embodiments may include an anomaly type indicator and some embodiments may include a shape indicator.

Abstract: A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers.

Abstract: A system for testing semiconductor components contained on a substrate, such as a wafer, a panel, a leadframe or a module, includes an interconnect configured to electrically engage all of the components on the substrate at the same time. The interconnect includes a switching network configured to selectively apply test signals to selected components, to electrically isolate defective components and to transmit test signals from selected groups of components. The system also includes a test apparatus, such as a wafer prober or a carrier for handling the substrate. A method for testing includes the steps of providing the interconnect having the switching network, and controlling test signals to the components using the switching network to perform various test procedures, such as functionality tests, parametric tests and burn-in tests.

Abstract: A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers.

Abstract: A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers.

Abstract: A system for testing semiconductor components contained on a substrate, such as a wafer, a panel, a leadframe or a module, includes an interconnect configured to electrically engage all of the components on the substrate at the same time. The interconnect includes a switching network configured to selectively apply test signals to selected components, to electrically isolate defective components and to transmit test signals from selected groups of components. The system also includes a test apparatus, such as a wafer prober or a carrier for handling the substrate. A method for testing includes the steps of providing the interconnect having the switching network, and controlling test signals to the components using the switching network to perform various test procedures, such as functionality tests, parametric tests and burn-in tests.

Abstract: A system for testing semiconductor components contained on a substrate, such as a wafer, a panel, a leadframe or a module, includes an interconnect configured to electrically engage all of the components on the substrate at the same time. The interconnect includes a switching network configured to selectively apply test signals to selected components, to electrically isolate defective components and to transmit test signals from selected groups of components. The system also includes a test apparatus, such as a wafer prober or a carrier for handling the substrate. A method for testing includes the steps of providing the interconnect having the switching network, and controlling test signals to the components using the switching network to perform various test procedures, such as functionality tests, parametric tests and burn-in tests.

Abstract: A system for testing semiconductor components contained on a substrate, such as a wafer, a panel, a leadframe or a module, includes an interconnect configured to electrically engage all of the components on the substrate at the same time. The interconnect includes a switching network configured to selectively apply test signals to selected components, to electrically isolate defective components and to transmit test signals from selected groups of components. The system also includes a test apparatus, such as a wafer prober or a carrier for handling the substrate. A method for testing includes the steps of providing the interconnect having the switching network, and controlling test signals to the components using the switching network to perform various test procedures, such as functionality tests, parametric tests and burn-in tests.

Abstract: An interconnect, a test system, and a test method for testing bumped semiconductor components, such as dice and packages, contained on substrates, such as wafers or panels, are provided. The test system includes the interconnect, a tester for generating test signals, and a wafer prober for placing the components and interconnect in physical contact. The interconnect includes interconnect contacts, such as conductive pockets, for electrically engaging bumped component contacts on the components. The interconnect also includes an on board multiplex circuit adapted to fan out and selectively transmit test signals from the tester to the interconnect contacts. The multiplex circuit expands tester resources by allowing test signals to be written to multiple components in parallel. Reading of the test signals from the components can be performed in groups up to the limit of the tester resources.

Abstract: An interconnect, a test system, and a test method for testing bumped semiconductor components, such as dice and packages, contained on substrates, such as wafers or panels, are provided. The test system includes the interconnect, a tester for generating test signals, and a wafer prober for placing the components and interconnect in physical contact. The interconnect includes interconnect contacts, such as conductive pockets, for electrically engaging bumped component contacts on the components. The interconnect also includes an on board multiplex circuit adapted to fan out and selectively transmit test signals from the tester to the interconnect contacts. The multiplex circuit expands tester resources by allowing test signals to be written to multiple components in parallel. Reading of the test signals from the components can be performed in groups up to the limit of the tester resources.

Abstract: A probe card for testing semiconductor wafers includes probe card contacts for electrically engaging die contacts on the wafer. The probe card also includes an on board multiplex circuit adapted to fan out and selectively transmit test signals from a tester to the probe card contacts. The multiplex circuit expands tester resources by allowing test signals to be written to multiple dice in parallel. Reading of the dice can be performed in groups up to the limit of the tester resources. In addition to expanding tester resources, the multiplex circuit maintains the individuality of each die, and permits defective dice to be electrically disconnected.

Abstract: A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers.

Abstract: A probe card for testing a semiconductor wafer, a test method, and a test system employing the probe card are provided. The probe card includes: a substrate; patterns of pin contacts slidably mounted to the substrate; and a force applying member for biasing the pin contacts into electrical contact with die contacts on the wafer. In an illustrative embodiment the force applying member includes spring loaded electrical connectors in physical and electrical contact with the pin contacts. Alternately, the force applying member includes a compressible pad for multiple pin contacts, or separate compressible pads for each pin contact. A penetration depth of the pin contacts into the die contacts is controlled by selecting a spring force of the force applying member, and an amount of Z-direction overdrive of the pin contacts into the die contacts.

Abstract: An interconnect, a test system, and a test method for testing bumped semiconductor components, such as dice and packages, contained on substrates, such as wafers or panels, are provided. The test system includes the interconnect, a tester for generating test signals, and a wafer prober for placing the components and interconnect in physical contact. The interconnect includes interconnect contacts, such as conductive pockets, for electrically engaging bumped component contacts on the components. The interconnect also includes an on board multiplex circuit adapted to fan out and selectively transmit test signals from the tester to the interconnect contacts. The multiplex circuit expands tester resources by allowing test signals to be written to multiple components in parallel. Reading of the test signals from the components can be performed in groups up to the limit of the tester resources.

Abstract: A probe card, a test method and a test system for testing semiconductor wafers are provided. The test system includes the probe card, a tester for generating test signals, and a wafer prober for placing the wafers and probe card in physical contact. The probe card includes contacts for electrically engaging die contacts on the wafer. The probe card also includes an on board multiplex circuit adapted to fan out and selectively transmit test signals from the tester to the probe card contacts. The multiplex circuit expands tester resources by allowing test signals to be written to multiple dice in parallel. Reading of the dice can be performed in groups up to the limit of the tester resources. In addition to expanding tester resources, the multiplex circuit maintains the individuality of each die, and permits defective dice to be electrically disconnected.

Abstract: A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers.

Abstract: A probe card for testing a semiconductor wafer, a test method, and a test system employing the probe card are provided. The probe card includes: a substrate; patterns of pin contacts slidably mounted to the substrate; and a force applying member for biasing the pin contacts into electrical contact with die contacts on the wafer. In an illustrative embodiment the force applying member includes spring loaded electrical connectors in physical and electrical contact with the pin contacts. Alternately, the force applying member includes a compressible pad for multiple pin contacts, or separate compressible pads for each pin contact. A penetration depth of the pin contacts into the die contacts is controlled by selecting a spring force of the force applying member, and an amount of Z-direction overdrive of the pin contacts into the die contacts.

Abstract: A probe card, a test method and a test system for testing semiconductor wafers are provided. The test system includes the probe card, a tester for generating test signals, and a wafer prober for placing the wafers and probe card in physical contact. The probe card includes contacts for electrically engaging die contacts on the wafer. The probe card also includes an on board multiplex circuit adapted to fan out and selectively transmit test signals from the tester to the probe card contacts. The multiplex circuit expands tester resources by allowing test signals to be written to multiple dice in parallel. Reading of the dice can be performed in groups up to the limit of the tester resources. In addition to expanding tester resources, the multiplex circuit maintains the individuality of each die, and permits defective dice to be electrically disconnected.

Abstract: A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers.