Patents by Inventor Calogero D. Presti

Calogero D. Presti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9331720
    Abstract: An output circuit with an integrated directional coupler and impedance matching circuit is disclosed. In an exemplary design, an apparatus includes a switchplexer and an output circuit. The switchplexer is coupled to at least one power amplifier. The output circuit is coupled to the switchplexer and a load (e.g., an antenna) and includes a directional coupler and an impedance matching circuit sharing at least one inductor. The output circuit performs impedance matching for the load. The output circuit also acts as a directional coupler and provides an input radio frequency (RF) signal as an output RF signal and further couples a portion of the input RF signal as a coupled RF signal. Reusing the at least one inductor for both the directional coupler and the impedance matching circuit may reduce circuitry, size, and cost of the wireless device and may also improve performance.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: May 3, 2016
    Assignee: QUALCOMM Incorporated
    Inventor: Calogero D. Presti
  • Publication number: 20150042412
    Abstract: Techniques for efficiently integrating directional coupler circuitry with other circuit elements of an RF front end. In an aspect, one or more inductors of an RF front end filter is incorporated into a first inductor of the directional coupler, and a capacitor is further coupled in parallel with the first inductor. In another aspect, circuitry associated with matching components of the RF front end may further be incorporated into the directional coupler design. Further techniques are provided for coupling directivity tuning elements to a second inductor of the directional coupler to improve the linearity of the coupler over other tuning techniques.
    Type: Application
    Filed: August 7, 2013
    Publication date: February 12, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: James Francis Imbornone, Yanjie Sun, Zhenying Luo, Zhenqi Chen, Calogero D. Presti, Xinwei Wang, Dong Zhang
  • Patent number: 8803615
    Abstract: An impedance matching circuit with at least one tunable notch filter for a power amplifier is disclosed. The power amplifier amplifies an input radio frequency (RF) signal and provides an amplified RF signal. The impedance matching circuit performs output impedance matching for the power amplifier and includes at least one tunable notch filter. Each tunable notch filter has a notch that can be varied in frequency to provide better attenuation of an undesired signal. The at least one tunable notch filter attenuates at least one undesired signal in the amplified RF signal. The at least one tunable notch filter may include (i) a first tunable notch filter to attenuate a first undesired signal at a second harmonic of the amplified RF signal and/or (ii) a second tunable notch filter to attenuate a second undesired signal at a third harmonic of the amplified RF signal.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: August 12, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Jose Cabanillas, Calogero D. Presti, Babak Nejati, Guy Klemens
  • Patent number: 8786373
    Abstract: Techniques for bypassing a supply voltage for an amplifier are disclosed. In an exemplary design, an apparatus includes an amplifier and an adjustable bypass circuit. The amplifier (e.g., a power amplifier) receives a supply voltage from a supply source. The adjustable bypass circuit is coupled to the supply source and provides bypassing for the supply voltage. The adjustable bypass circuit includes an adjustable capacitor or a fixed capacitor coupled to an adjustable resistor. The supply source may be (i) a power supply source providing a fixed supply voltage for the amplifier or (ii) an envelope tracker providing a variable supply voltage for the amplifier.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: July 22, 2014
    Inventors: Calogero D. Presti, Jose Cabanillas
  • Patent number: 8773204
    Abstract: Techniques for reducing undesired source degeneration inductance are disclosed. In an exemplary design, an apparatus includes first and second connections. The first connection includes a first parasitic inductance acting as a source degeneration inductance of an amplifier. The second connection includes a second parasitic inductance magnetically coupled to the first parasitic inductance to reduce the source degeneration inductance of the amplifier. The amplifier (e.g., a single-ended power amplifier) may be coupled to circuit ground via the first connection. An impedance matching circuit may be coupled to the amplifier and may include a circuit component coupled to circuit ground via the second connection. The first connection may be located sufficiently close to (e.g., within a predetermined distance of) the second connection in order to obtain the desired magnetic coupling between the first and second parasitic inductances.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: July 8, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Jose Cabanillas, Calogero D Presti, Norman L Frederick, Jr.
  • Patent number: 8686796
    Abstract: Amplifiers with improved efficiency and output power are described. In an exemplary design, an apparatus includes an amplifier having at least three transistors and at least two capacitors. The at least three transistors are coupled in a stack and receive and amplify an input signal and provide an output signal. The at least two capacitors include at least one capacitor coupled between the drain and source of an associated transistor for each of at least two transistors in the stack, e.g., at least one capacitor for each transistor in the stack except for the bottommost transistor in the stack. The at least two capacitors recycle energy from gate-to-source parasitic capacitors of the at least two transistors to the output signal, which improves efficiency and output power of the amplifier.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: April 1, 2014
    Assignee: QUALCOMM Incorporated
    Inventor: Calogero D. Presti
  • Publication number: 20130214862
    Abstract: Techniques for bypassing a supply voltage for an amplifier are disclosed. In an exemplary design, an apparatus includes an amplifier and an adjustable bypass circuit. The amplifier (e.g., a power amplifier) receives a supply voltage from a supply source. The adjustable bypass circuit is coupled to the supply source and provides bypassing for the supply voltage. The adjustable bypass circuit includes an adjustable capacitor or a fixed capacitor coupled to an adjustable resistor. The supply source may be (i) a power supply source providing a fixed supply voltage for the amplifier or (ii) an envelope tracker providing a variable supply voltage for the amplifier.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 22, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventors: Calogero D. Presti, Jose Cabanillas
  • Publication number: 20130207741
    Abstract: A programmable directional coupler to detect incident power and possibly reflected power is disclosed. The programmable directional coupler includes first and second inductors and at least one adjustable capacitor. The first inductor is coupled between first and second nodes, and the second inductor is coupled between third and fourth nodes of the programmable directional coupler. The second inductor is magnetically coupled to the first inductor and has a mutual inductance with the first inductor. The at least one adjustable capacitor is coupled between the first and second inductors. The programmable directional coupler may further include at least one fixed or adjustable capacitor coupled between at least one node among the first, second, third and fourth nodes and circuit ground. The programmable directional coupler may further include an adjustable resistor coupled between the fourth node and circuit ground.
    Type: Application
    Filed: February 13, 2012
    Publication date: August 15, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventor: Calogero D, Presti
  • Publication number: 20130207732
    Abstract: Techniques for reducing undesired source degeneration inductance are disclosed. In an exemplary design, an apparatus includes first and second connections. The first connection includes a first parasitic inductance acting as a source degeneration inductance of an amplifier. The second connection includes a second parasitic inductance magnetically coupled to the first parasitic inductance to reduce the source degeneration inductance of the amplifier. The amplifier (e.g., a single-ended power amplifier) may be coupled to circuit ground via the first connection. An impedance matching circuit may be coupled to the amplifier and may include a circuit component coupled to circuit ground via the second connection. The first connection may be located sufficiently close to (e.g., within a predetermined distance of) the second connection in order to obtain the desired magnetic coupling between the first and second parasitic inductances.
    Type: Application
    Filed: February 14, 2012
    Publication date: August 15, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventors: Jose Cabanillas, Calogero D. Presti, Norman L. Frederick, JR.
  • Publication number: 20130194054
    Abstract: An output circuit with an integrated directional coupler and impedance matching circuit is disclosed. In an exemplary design, an apparatus includes a switchplexer and an output circuit. The switchplexer is coupled to at least one power amplifier. The output circuit is coupled to the switchplexer and a load (e.g., an antenna) and includes a directional coupler and an impedance matching circuit sharing at least one inductor. The output circuit performs impedance matching for the load. The output circuit also acts as a directional coupler and provides an input radio frequency (RF) signal as an output RF signal and further couples a portion of the input RF signal as a coupled RF signal. Reusing the at least one inductor for both the directional coupler and the impedance matching circuit may reduce circuitry, size, and cost of the wireless device and may also improve performance.
    Type: Application
    Filed: January 30, 2012
    Publication date: August 1, 2013
    Applicant: QUALCOMM Incorporated
    Inventor: Calogero D. Presti
  • Publication number: 20130187712
    Abstract: An impedance matching circuit with at least one tunable notch filter for a power amplifier is disclosed. The power amplifier amplifies an input radio frequency (RF) signal and provides an amplified RF signal. The impedance matching circuit performs output impedance matching for the power amplifier and includes at least one tunable notch filter. Each tunable notch filter has a notch that can be varied in frequency to provide better attenuation of an undesired signal. The at least one tunable notch filter attenuates at least one undesired signal in the amplified RF signal. The at least one tunable notch filter may include (i) a first tunable notch filter to attenuate a first undesired signal at a second harmonic of the amplified RF signal and/or (ii) a second tunable notch filter to attenuate a second undesired signal at a third harmonic of the amplified RF signal.
    Type: Application
    Filed: January 23, 2012
    Publication date: July 25, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventors: Jose Cabanillas, Calogero D. Presti, Babak Nejati, Guy Klemens
  • Publication number: 20120268205
    Abstract: Amplifiers with improved efficiency and output power are described. In an exemplary design, an apparatus includes an amplifier having at least three transistors and at least two capacitors. The at least three transistors are coupled in a stack and receive and amplify an input signal and provide an output signal. The at least two capacitors include at least one capacitor coupled between the drain and source of an associated transistor for each of at least two transistors in the stack, e.g., at least one capacitor for each transistor in the stack except for the bottommost transistor in the stack. The at least two capacitors recycle energy from gate-to-source parasitic capacitors of the at least two transistors to the output signal, which improves efficiency and output power of the amplifier.
    Type: Application
    Filed: April 19, 2011
    Publication date: October 25, 2012
    Applicant: QUALCOMM INCORPORATED
    Inventor: Calogero D. Presti