Abstract: A system, method and computer program product for extracting integrated circuit on-chip parasitic capacitance in semiconductor structures including structures formed according to a Self-Aligned Double Patterning (SADP) semiconductor manufacturing process. A method of calculating the capacitance of a conductive signal wire in a SADP layer whose adjacent wires or groups of wires are floating (not connected to a circuit or net and not signal carrying). Further, there is provided a system running an iterative method for accurately and efficiently eliminating a group of floating metals by eliminating one floating metal wire per iteration while extracting its corresponding on-chip parasitic coupling capacitance effect. Further, system and methods calculate parasitic capacitance calculation for an “isolated” wire(s) or a “semi-isolated wire” resulting from employing a Self-Aligned Double Patterning (SADP) processing technique.

Abstract: A system, method and computer program product for extracting integrated circuit on-chip parasitic capacitance in semiconductor structures including structures formed according to a Self-Aligned Double Patterning (SADP) semiconductor manufacturing process. A method of calculating the capacitance of a conductive signal wire in a SADP layer whose adjacent wires or groups of wires are floating (not connected to a circuit or net and not signal carrying). Further, there is provided a system running an iterative method for accurately and efficiently eliminating a group of floating metals by eliminating one floating metal wire per iteration while extracting its corresponding on-chip parasitic coupling capacitance effect. Further, system and methods calculate parasitic capacitance calculation for an “isolated” wire(s) or a “semi-isolated wire” resulting from employing a Self-Aligned Double Patterning (SADP) processing technique.

Abstract: A method, system and program product are disclosed for statistical modeling an integrated circuit that provides information about partial correlations between model parameters. The invention determines a variance-covariance matrix for data to be modeled; conducts principal component analysis on the variance-covariance matrix; and creates a statistical model with an independent distribution for each principal component, allowing calculation of each individual model parameter as a weighted sum by a circuit simulator. The statistical model provides information about how well individual transistors will track one another based on layout similarity. This allows the designer to quantify and take advantage of design practices that make all transistors similar, for example, by orienting all gates in the same direction. A method, system and program product for simulating a circuit using the statistical model are also included.