Patents by Inventor Camelia Rusu
Camelia Rusu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230149931Abstract: Embodiments of the present disclosure are directed to an array substrate which can be used in nucleic acid sequencing, which includes a plurality of fiducial domains (FDs). The disclosure also includes array substrate manufacturing methods and methods for making FDs on such substrates.Type: ApplicationFiled: April 23, 2021Publication date: May 18, 2023Inventors: Camelia RUSU, Huawen WU, Joshua Dale BAKER, Jeffrey MARKS, Wesley C. CHANG, Dae KIM
-
Patent number: 9865472Abstract: A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine containing gas is provided. A plasma is provided from the etch gas. Then, the flow of the etch gas is stopped.Type: GrantFiled: April 20, 2016Date of Patent: January 9, 2018Assignee: Lam Research CorporationInventors: Robert Chebi, Frank Lin, Jaroslaw W. Winniczek, Wan-Lin Chen, Erin Moore, Lily Zheng, Stephan Lassig, Jeff Bogart, Camelia Rusu
-
Patent number: 9514955Abstract: A method for processing a substrate includes providing the substrate including a photoresist/bottom anti-reflection coating (PR/BARC) layer, a hard mask layer, a stop layer, a carbon layer and a stack including a plurality of layers. The method includes defining a hole pattern including a plurality of holes in the PR/BARC layer using photolithography; transferring the hole pattern into the carbon layer; filling the plurality of holes in the hole pattern with oxide to create oxide pillars; using a planarization technique to remove the hard mask layer, a remaining portion of the PR/BARC layer and the stop layer; stripping the carbon layer to expose the oxide pillars; filling space between the oxide pillars with hard a mask material including metal; planarizing at least part of the hard mask material; and stripping the oxide pillars to expose the hole pattern in the hard mask material.Type: GrantFiled: May 14, 2015Date of Patent: December 6, 2016Assignee: LAM RESEARCH CORPORATIONInventors: Joydeep Guha, Camelia Rusu
-
Publication number: 20160233102Abstract: A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine containing gas is provided. A plasma is provided from the etch gas. Then, the flow of the etch gas is stopped.Type: ApplicationFiled: April 20, 2016Publication date: August 11, 2016Inventors: Robert CHEBI, Frank LIN, Jaroslaw W. WINNICZEK, Wan-Lin CHEN, Erin MOORE, Lily ZHENG, Stephan LASSIG, Jeff BOGART, Camelia RUSU
-
Patent number: 9330926Abstract: A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine containing gas is provided. A plasma is provided from the etch gas. Then, the flow of the etch gas is stopped.Type: GrantFiled: December 18, 2008Date of Patent: May 3, 2016Assignee: Lam Research CorporationInventors: Robert Chebi, Frank Lin, Jaroslaw W. Winniczek, Wan-Lin Chen, Erin McDonnell, Lily Zheng, Stephan Lassig, Jeff Bogart, Camelia Rusu
-
Patent number: 9267605Abstract: A pressure control valve assembly of a plasma processing chamber in which semiconductor substrates are processed includes a housing having an inlet, an outlet and a conduit extending between the inlet and the outlet, the inlet adapted to be connected to an interior of the plasma processing chamber and the outlet adapted to be connected to a vacuum pump which maintains the plasma processing chamber at desired pressure set points during rapid alternating phases of processing a semiconductor substrate in the chamber. A fixed slotted valve plate having a first set of parallel slots therein is fixed in the conduit such that gasses withdrawn from the chamber into the conduit pass through the first set of parallel slots. A movable slotted valve plate having a second set of parallel slots therein is movable with respect to the fixed slotted valve plate so as to adjust pressure in the chamber.Type: GrantFiled: November 7, 2011Date of Patent: February 23, 2016Assignee: LAM RESEARCH CORPORATIONInventors: Mirzafer Abatchev, Camelia Rusu, Brian McMillin
-
Publication number: 20150364337Abstract: A method for processing a substrate includes providing the substrate including a photoresist/bottom anti-reflection coating (PR/BARC) layer, a hard mask layer, a stop layer, a carbon layer and a stack including a plurality of layers. The method includes defining a hole pattern including a plurality of holes in the PR/BARC layer using photolithography; transferring the hole pattern into the carbon layer; filling the plurality of holes in the hole pattern with oxide to create oxide pillars; using a planarization technique to remove the hard mask layer, a remaining portion of the PR/BARC layer and the stop layer; stripping the carbon layer to expose the oxide pillars; filling space between the oxide pillars with hard a mask material including metal; planarizing at least part of the hard mask material; and stripping the oxide pillars to expose the hole pattern in the hard mask material.Type: ApplicationFiled: May 14, 2015Publication date: December 17, 2015Inventors: Joydeep Guha, Camelia Rusu
-
Patent number: 8871105Abstract: A method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak.Type: GrantFiled: March 9, 2012Date of Patent: October 28, 2014Assignee: Lam Research CorporationInventors: Jaroslaw W. Winniczek, Frank Y. Lin, Alan J. Miller, Qing Xu, Seongjun Heo, Jin Hwan Ham, Sang Joon Yoon, Camelia Rusu
-
Patent number: 8691698Abstract: A method for etching features in a silicon layer disposed below a mask in a plasma processing chamber a plurality of cycles is provided. A deposition phase forming a deposition on the silicon layer in the plasma processing chamber is provided comprising providing a deposition gas into the plasma processing chamber wherein the deposition gas comprises a halogen containing etchant component and a fluorocarbon deposition component, forming the deposition gas into a plasma, which provides a net deposition on the silicon layer, and stopping the flow of the deposition gas. A silicon etch phase is provided, comprising providing a silicon etch gas into the plasma processing chamber that is different than the deposition gas, forming the silicon etch gas into a plasma to etch the silicon layer, and stopping the flow of the silicon etch gas.Type: GrantFiled: February 8, 2012Date of Patent: April 8, 2014Assignee: Lam Research CorporationInventors: Qing Xu, William Thie, Camelia Rusu
-
Patent number: 8609548Abstract: A method for etching features into an etch layer in a plasma processing chamber, comprising a plurality of cycles is provided. Each cycle comprises a deposition phase and an etching phase. The deposition phase comprises providing a flow of deposition gas, forming a plasma from the deposition gas in the plasma processing chamber, providing a first bias during the deposition phase to provide an anisotropic deposition, and stopping the flow of the deposition gas into the plasma processing chamber. The etching phase, comprises providing a flow of an etch gas, forming a plasma from the etch gas in the plasma processing chamber, providing a second bias during the etch phase, wherein the first bias is greater than the second bias, and stopping the flow of the etch gas into the plasma processing chamber.Type: GrantFiled: July 21, 2011Date of Patent: December 17, 2013Assignee: Lam Research CorporationInventors: Qing Xu, Camelia Rusu, Jaroslaw W. Winniczek, Frank Y. Lin, Alan J. Miller
-
Patent number: 8574447Abstract: A method for etching features into a silicon substrate disposed below a mask in a plasma processing chamber is provided. The silicon substrate is etched through the mask comprising a plurality of cycles, wherein each cycle comprises a sidewall deposition phase and an etch phase. The sidewall deposition phase comprises providing a flow of sidewall inorganic deposition phase gas comprising a silicon containing compound gas and at least one of oxygen, nitrogen or NOx, into the plasma processing chamber, forming a plasma from the sidewall deposition phase gas in the plasma processing chamber, and stopping the flow of the sidewall deposition gas into the plasma processing chamber. The etch phase comprises, providing a flow of an etching gas comprising a halogen component, forming a plasma from the etching gas in the plasma processing chamber, and stopping the flow of the etching gas.Type: GrantFiled: March 31, 2010Date of Patent: November 5, 2013Assignee: Lam Research CorporationInventors: Tsuyoshi Aso, Camelia Rusu
-
Publication number: 20130237062Abstract: A method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak.Type: ApplicationFiled: March 9, 2012Publication date: September 12, 2013Inventors: Jaroslaw W. Winniczek, Frank Y. Lin, Alan J. Miller, Qing Xu, Seongjun Heo, Jin Hwan Ham, Sang Joon Yoon, Camelia Rusu
-
Publication number: 20130203256Abstract: A method for etching features in a silicon layer disposed below a mask in a plasma processing chamber a plurality of cycles is provided. A deposition phase forming a deposition on the silicon layer in the plasma processing chamber is provided comprising providing a deposition gas into the plasma processing chamber wherein the deposition gas comprises a halogen containing etchant component and a fluorocarbon deposition component, forming the deposition gas into a plasma, which provides a net deposition on the silicon layer, and stopping the flow of the deposition gas. A silicon etch phase is provided, comprising providing a silicon etch gas into the plasma processing chamber that is different than the deposition gas, forming the silicon etch gas into a plasma to etch the silicon layer, and stopping the flow of the silicon etch gas.Type: ApplicationFiled: February 8, 2012Publication date: August 8, 2013Applicant: LAM RESEARCH CORPORATIONInventors: Qing Xu, William Thie, Camelia Rusu
-
Patent number: 8440473Abstract: A method for etching features into an etch layer in a plasma processing chamber is provided. An optically timed deposition phase is provided comprising providing a flow of deposition phase gas, detecting the presence of deposition gas within the plasma processing chamber, providing RF energy for forming a plasma from the deposition phase gas in the plasma processing chamber, and stopping the flow of the deposition gas into the plasma processing chamber. An optically timed etching phase is provided, comprising providing a flow of an etch gas, detecting the presence of the etch gas within the plasma processing chamber, providing RF energy for forming a plasma from the etch gas in the plasma processing chamber, and stopping the flow of the etch gas into the plasma processing chamber.Type: GrantFiled: June 6, 2011Date of Patent: May 14, 2013Assignee: Lam Research CorporationInventors: Qing Xu, Camelia Rusu, Brian K. McMillin, Alexander M. Paterson
-
Publication number: 20130115776Abstract: A pressure control valve assembly of a plasma processing chamber in which semiconductor substrates are processed includes a housing having an inlet, an outlet and a conduit extending between the inlet and the outlet, the inlet adapted to be connected to an interior of the plasma processing chamber and the outlet adapted to be connected to a vacuum pump which maintains the plasma processing chamber at desired pressure set points during rapid alternating phases of processing a semiconductor substrate in the chamber. A fixed slotted valve plate having a first set of parallel slots therein is fixed in the conduit such that gasses withdrawn from the chamber into the conduit pass through the first set of parallel slots. A movable slotted valve plate having a second set of parallel slots therein is movable with respect to the fixed slotted valve plate so as to adjust pressure in the chamber.Type: ApplicationFiled: November 7, 2011Publication date: May 9, 2013Applicant: Lam Research CorporationInventors: Mirzafer Abatchev, Camelia Rusu, Brian McMillin
-
Publication number: 20120309194Abstract: A method for etching features into an etch layer in a plasma processing chamber, comprising a plurality of cycles is provided. Each cycle comprises a deposition phase and an etching phase. The deposition phase comprises providing a flow of deposition gas, forming a plasma from the deposition gas in the plasma processing chamber, providing a first bias during the deposition phase to provide an anisotropic deposition, and stopping the flow of the deposition gas into the plasma processing chamber. The etching phase, comprises providing a flow of an etch gas, forming a plasma from the etch gas in the plasma processing chamber, providing a second bias during the etch phase, wherein the first bias is greater than the second bias, and stopping the flow of the etch gas into the plasma processing chamber.Type: ApplicationFiled: July 21, 2011Publication date: December 6, 2012Applicant: LAM RESEARCH CORPORATIONInventors: Qing Xu, Camelia Rusu, Jaroslaw W. Winniczek, Frank Y. Lin, Alan J. Miller
-
Publication number: 20120309198Abstract: A method for etching features into an etch layer in a plasma processing chamber is provided. An optically timed deposition phase is provided comprising providing a flow of deposition phase gas, detecting the presence of deposition gas within the plasma processing chamber, providing RF energy for forming a plasma from the deposition phase gas in the plasma processing chamber, and stopping the flow of the deposition gas into the plasma processing chamber. An optically timed etching phase is provided, comprising providing a flow of an etch gas, detecting the presence of the etch gas within the plasma processing chamber, providing RF energy for forming a plasma from the etch gas in the plasma processing chamber, and stopping the flow of the etch gas into the plasma processing chamber.Type: ApplicationFiled: June 6, 2011Publication date: December 6, 2012Applicant: LAM RESEARCH CORPORATIONInventors: Qing Xu, Camelia Rusu, Brian K. McMillin, Alexander M. Paterson
-
Publication number: 20110244686Abstract: A method for etching features into a silicon substrate disposed below a mask in a plasma processing chamber is provided. The silicon substrate is etched through the mask comprising a plurality of cycles, wherein each cycle comprises a sidewall deposition phase and an etch phase. The sidewall deposition phase comprises providing a flow of sidewall inorganic deposition phase gas comprising a silicon containing compound gas and at least one of oxygen, nitrogen or NOx, into the plasma processing chamber, forming a plasma from the sidewall deposition phase gas in the plasma processing chamber, and stopping the flow of the sidewall deposition gas into the plasma processing chamber. The etch phase comprises, providing a flow of an etching gas comprising a halogen component, forming a plasma from the etching gas in the plasma processing chamber, and stopping the flow of the etching gas.Type: ApplicationFiled: March 31, 2010Publication date: October 6, 2011Applicant: Lam Research CorporationInventors: Tsuyoshi Aso, Camelia Rusu
-
Publication number: 20100327413Abstract: A method for opening a carbon-based hardmask layer formed on an etch layer over a substrate is provided. The hardmask layer is disposed below a patterned mask. The substrate is placed in a plasma processing chamber. The hardmask layer is opened by flowing a hardmask opening gas including a COS component into the plasma chamber, forming a plasma from the hardmask opening gas, and stopping the flow of the hardmask opening gas. The hardmask layer may be made of amorphous carbon, or made of spun-on carbon, and the hardmask opening gas may further include O2.Type: ApplicationFiled: May 2, 2008Publication date: December 30, 2010Applicant: LAM RESEARCH CORPORATIONInventors: Jong Pil Lee, Seiji Kawaguchi, Camelia Rusu, Zhisong Huang, Mukund Srinivasan, Eric Hudson, Aaron Eppler
-
Patent number: 7785753Abstract: Disclosed is a method for processing a two layer mask for use in fabrication of semiconductor devices whereby the critical dimension (CD) of a semiconductor device being fabricated with the mask can be controlled. After forming a carbon mask layer and a silicon containing photoresist layer on the carbon mask, a two-step process forms openings in the carbon mask layer, as required for subsequent device fabrication. The structure is placed in a plasma processing chamber, and an oxygen plasma is employed to partially etch the carbon layer. The oxygen plasma reacts with silicon in the photoresist to form a hard silicon oxide layer on the surface of the photoresist. A hydrogen plasma is then employed to complete the etch through the carbon layer with a reduced critical dimension. Damage to the silicon containing photoresist layer is kept to a minimum during the plasma etch process by limiting the low frequency RF power.Type: GrantFiled: May 17, 2006Date of Patent: August 31, 2010Assignee: Lam Research CorporationInventors: Yoojin Kim, Camelia Rusu, Jonathan Kim