Abstract: An improved memory module structure for use in a large memory in which, before operational use, the memory modules are tested and configured by a process that requires storing logical page addresses into a page register in each module. In this module, page address data are input to the page register from a data input line to the module. Since there is a separate data input line for each module in a column of such modules, and since the data input lines are not used to carry data to the memory in a test and configuration mode, the data input lines can be used to supply page address data simultaneously to the page registers of an entire column of modules. This avoids having to address each module in the column individually, and reduces testing an configuration time by a factor equal to the number of modules in a column. The complexity of each module is also reduced by obviating the need for individual module addressing in the test mode.

Abstract: A memory circuit for controlling writing and reading operations in a large semiconductor memory having multiple modules, some of which are subject to production or environmentally caused defects. Memory modules are arranged in columns and there is a column interface for each column, each module being connected to its column interface by a single-bit data line. Each column interface includes a configuration register that is used to record an association between the memory modules in the column and selected data bit positions of an external data word. The same association is used both during writing operations, wherein data words are written from the data bus to the memory modules, and during reading operations, wherein data words are read from the memory modules to the data bus.