Abstract: This application relates to display panels, methods of driving the same, and display devices. The display panel includes: a first pixel circuit and a demultiplexing circuit. The first pixel circuit includes a first reset circuit, a first data writing circuit, and a first drive circuit. A first terminal of the first reset circuit is connected to a first terminal of the first drive circuit. A second terminal of the first reset circuit is connected to a first multiplexing signal line. A control terminal of the first drive circuit is connected to a first terminal of the first data writing circuit. A second terminal of the first data writing circuit is connected to the first multiplexing signal line. The demultiplexing circuit includes a first control circuit and a second control circuit. A first terminal of the first control circuit is connected to the first multiplexing signal line. A second terminal of the first control circuit is used for receiving a reset signal.

Abstract: A multiplexer circuit includes a first selection sub-circuit and a second selection sub-circuit. The first selection sub-circuit configured to transmit an input signal received at a input signal terminal to a first output terminal in response to a first control signal received at a first control terminal, and transmit a voltage of a power supply voltage terminal to the first output terminal in response to a second control signal received at a second control terminal. The second selection sub-circuit configured to transmit the input signal received at the input signal terminal to a second output terminal in response to a third control signal received at a third control terminal, and transmit the voltage of the power supply voltage terminal to the second output terminal in response to a fourth control signal received at a fourth control terminal.

Abstract: A display substrate has a display area and a peripheral area. The display substrate includes a plurality of sub-pixels, a plurality of groups of gate scan signal lines, and a plurality of groups of data lines. Each group of gate scan signal lines includes at least one gate scan signal line, each group of data lines includes n data lines, and the plurality of sub-pixels are arranged in an array; and n is greater than or equal to 2. A group of gate scan signal lines is electrically connected to n rows of sub-pixels. A column of sub-pixels is electrically connected to a group of data lines, and includes a plurality of groups of sub-pixels. Each group of sub-pixels includes n sub-pixels. The n sub-pixels are respectively electrically connected to n data lines in the group of data lines to which this column of sub-pixels is electrically connected.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. At least one sub-pixel includes a storage capacitor. The storage capacitor includes a second capacitor electrode, a first capacitor electrode and a third capacitor electrode which are sequentially on the base substrate. The first capacitor electrode has a first capacitor electrode side and a second capacitor electrode side opposite to each other in the second direction, and the second capacitor electrode has a third capacitor electrode side and a fourth capacitor electrode side opposite to each other in the second direction; orthographic projections of the first capacitor electrode side and the second capacitor electrode side on the base substrate are between an orthographic projection of the third capacitor electrode side and an orthographic projection of the fourth capacitor electrode side on the base substrate.

Abstract: The present disclosure provides a display substrate and a display device, and belongs to the field of display technology. The display substrate of the present disclosure has a display region, and includes a base and a plurality of data lines and a plurality of fan-out traces on the base; each of the plurality of data lines is connected to a corresponding one of the plurality of fan-out traces at a connection node in the display region; and at least one of the plurality of data lines is connected to a corresponding fan-out trace at a plurality of connection nodes.

Abstract: A display substrate, including: a base, and a plurality of sub-pixels arranged on the base. At least one of the plurality of sub-pixels includes a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit. The pixel driving circuit includes a plurality of transistors and at least one storage capacitor. In a direction perpendicular to the base, the display substrate includes: a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer, which are sequentially arranged on the base. The semiconductor layer includes: an active layer of the plurality of transistors. The first metal layer includes at least a scanning line extending in a first direction, a gate electrode of the plurality of transistors, and a first capacitor electrode plate of the storage capacitor.

Abstract: Provided are a display substrate and a display device. The display substrate includes a base substrate, and gate lines extending in a first direction, data lines extending in a second direction and pixel units that are on the base substrate, the first direction intersecting the second direction; each pixel unit including sub-pixels, each sub-pixel including a pixel circuit; the pixel circuit including at least a switching transistor, a drive transistor, a sensing transistor, and a storage capacitor; for each pixel circuit, the switching transistor, the drive transistor, and the sensing transistor therein are all on a same side of the storage capacitor; the switching transistor is at an intersection of the gate line and the data line connected thereto, and the switching transistor is adjacent to the sensing transistor in the first direction and adjacent to the drive transistor in the second direction.

Abstract: A display substrate and a manufacturing method thereof, and a display panel are provided. The display substrate includes a base substrate having a display region and a peripheral region adjacent to the display region, the peripheral region being provided therein with a gate driver-on-array circuit including a plurality of transistors and capacitors, all of the transistors are provided in a transistor region, at least a part of the plurality of capacitors are provided in a capacitor region, and the capacitor region is located on a side of the transistor region distal to the display region; and an encapsulation structure for encapsulating the display region and the transistor region together; the peripheral region further including a sealing region for arranging a sealing structure therein, the capacitor region is located in the sealing region, and the sealing region is provided on a side of the encapsulation structure distal to the display region.

Abstract: A display apparatus, a display panel, and a driving method thereof, and a method of detecting a pixel circuit are described. The display panel of the present disclosure includes a pixel unit and a detection apparatus, and the pixel unit includes a pixel circuit and a light-emitting element. The pixel circuit includes a first transistor, a second transistor, a driving transistor, and a storage capacitor. The detection device is configured to: turn off the first transistor and the second transistor, and detect an amount of current leakage of the driving transistor leaked through the sensing line to obtain a first current leakage parameter; detect a first characteristic parameter of the driving transistor to obtain a first reference characteristic parameter; and determine a first target characteristic parameter according to the first current leakage parameter and the first reference characteristic parameter.

Abstract: An array substrate includes: a substrate, at least one gate driving circuit and at least one clock signal line that are located on a same side of the substrate. The gate driving circuit includes a plurality of cascaded shift registers located in different rows, the plurality of shift registers are divided into at least two groups of shift registers, each group of shift registers includes at least one shift register, located in a same column. A gate driving circuit in the at least one gate driving circuit corresponds to at least one clock signal line. The clock signal line includes a main body transmission section configured to transmit a clock signal, and at least two branch transmission sections connected to the main body transmission section. Each branch transmission section is connected to a clock signal input terminal of each shift register in a respective group of shift registers.

Abstract: An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate, and a GOA circuit, a source electrode IC and PLG wires arranged on the base substrate, and the PLG wires connect the GOA circuit with the source electrode IC. The GOA circuit transmits a GOA signal, and the GOA signal comprises a cascade signal and a non-cascade signal. The PLG wires comprise a first PLG wire group and at least one second PLG wire group, the first PLG wire group transmits the cascade signal, the second PLG wire group transmits the non-cascade signal, a line width of the first PLG wire group is smaller than that of the second PLG wire group, and the first PLG wire group is located at a side of the second PLG wire group distal to an active area of the base substrate.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. At least one sub-pixel includes a first transistor, a second transistor and a storage capacitor. The display substrate further includes an extension portion protruding from the gate electrode of the first transistor, and the extension portion is extended from the gate electrode of the first transistor in the second direction; the extension portion is at least partially overlapped with the first electrode of the second transistor in a direction perpendicular to the base substrate and is electrically connected with the first electrode of the second transistor; in the first direction, the extension portion has a second side closest to the second capacitor electrode, and the second side is recessed in a direction away from the second capacitor electrode.

Abstract: The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a substrate, and a compensation electrode, an auxiliary electrode, a light-emitting functional layer, and a cathode layer arranged on one side of the substrate. The auxiliary electrode is arranged on one side of the compensation electrode away from the substrate, and coupled to the compensation electrode. A first notch is formed in a side surface of the auxiliary electrode, and at least a part of the first notch extends in a direction parallel to the substrate. The light-emitting functional layer is arranged on one side of the auxiliary electrode away from the substrate, and interrupted at the first notch. The cathode layer is arranged on one side of the light-emitting functional layer away from the substrate, and coupled to the auxiliary electrode at the first notch.

Abstract: The present disclosure provides a motherboard and a manufacturing method for the motherboard, the motherboard includes at least one display area, a periphery area surrounding the at least one display area, a plurality of test terminals, an electrostatic discharge line, a plurality of resistors and at least one thin film transistor. The plurality of test terminals are respectively electrically connected to the electrostatic discharge line through the plurality of resistors. At least one of the plurality of resistors includes an inorganic nonmetal trace. The at least one thin film transistor includes an active layer, and the inorganic nonmetal trace includes a same semiconductor matrix material as the active layer of the at least one thin film transistor.

Abstract: A display panel and an electronic device are provided. The display panel includes: a base substrate; a plurality of gate lines and a plurality of data lines located on the base substrate. A plurality of sub-pixel units are located on the base substrate, and at least one of the plurality of sub-pixel units includes a light-emitting element, a switching transistor, an induction transistor, a driving transistor and a storage transistor. In this sub-pixel unit, an orthographic projection of the switching transistor on the base substrate and an orthographic projection of the induction transistor on the base substrate are located on a first side of an orthographic projection of the storage capacitor on the base substrate. An orthographic projection of the driving transistor on the base substrate is located on a second side of the orthographic projection of the storage capacitor on the base substrate.

Abstract: A display substrate including a plurality of light emitting elements respectively in a plurality of subpixels configured to emit light for image display is provided. A respective one of the plurality of subpixels includes a base substrate; a first auxiliary cathode; a passivation layer; a first insulating layer; a second auxiliary cathode; a second insulating layer; and a pixel definition layer. The display substrate has a cathode aperture extending through the pixel definition layer and an auxiliary cathode aperture extending through the first insulating layer and the passivation layer. A cathode of a respective one of the plurality of light emitting elements extends into the cathode aperture to electrically connect with the second auxiliary cathode. The second auxiliary cathode extends into the auxiliary cathode aperture to electrically connect with the first auxiliary cathode.

Abstract: A display substrate and a display device are provided. The display substrate includes sub-pixels which are arranged in a sub-pixel array in a first direction and a second direction. At least one sub-pixel includes a first transistor, a second transistor, a third transistor, and a storage capacitor. An active layer of the third transistor includes a body region and a first via hole region successively arranged in the first direction and electrically connected with each other; a first electrode of the third transistor is electrically connected to the first via hole region through a first via hole which is shifted in the second direction with respect to the body region, allowing the active layer incudes a first active layer side connecting the body region and the first via hole region; an extension direction of the first active layer side intersects with both the first direction and the second direction.

Abstract: The present disclosure relates to the field of display technologies, and provides an array substrate, a manufacturing method thereof, and a display panel.

Abstract: Provided are a pixel circuit, a driving method thereof and a display panel. The pixel circuit includes: multiple sub-pixel circuits in an array; each sub-pixel circuit includes a first node control sub-circuit, a second node control sub-circuit, a driving sub-circuit, a storage sub-circuit, a reading sub-circuit and a light emitting device; at least reading sub-circuits of the sub-pixel circuits of some rows are controlled by a same sensing control line; the first node control sub-circuit charges the storage sub-circuit in response to a first scan signal; the second node control sub-circuit writes a reference voltage signal into a second node in response to a second scan signal; the reading sub-circuit reads a potential of the second node in response to a sensing control signal written by a sensing control line; the driving sub-circuit drives the light emitting device to emit light.

Abstract: An array substrate and a detection method thereof, and a display panel are disclosed. The array substrate includes a plurality of subpixels and a plurality of signal line structures. The plurality of subpixels are arranged in an array of a plurality of rows and a plurality of columns along a first direction and a second direction. Each signal line structure of the plurality of signal line structures includes at least one first detection line extending along the first direction; adjacent (n)th row and (n+1)th row of subpixels in the array form a subpixel row group, and the signal line structure is configured to be connected to the (n)th row and (n+1)th row of subpixels and detect electrical characteristics of first transistors or light-emitting elements in the subpixels.