Abstract: A method and system for input/output control in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously in response to one or more transfer requests. In response to a transfer request having a data address associated therewith, a particular target device is identified. The data address is then written into an address queue. Thereafter, one or more of the multiple sub-buses are utilized to transfer data to or from a single processor in response to a transfer request from a single processor. In response to a transfer request from multiple processors, one or more of the multiple sub-buses may be utilized separately to simultaneously transfer data to or from multiple processors.

Abstract: A method and system for arbitrating access to a component of a computer have been disclosed the method and system include an arbitration unit for granting access to the component; and a plurality of units for executing a plurality of transactions requiring access to the component. Each transaction of the plurality of transactions has an encoded priority. Each of the plurality of units further provide the arbitration unit with the encoded priority of each of the plurality of transactions. The arbitration unit grants a predetermined number of the plurality of units access to the component in response to the encoded priority of each of the predetermined plurality of transactions.

Abstract: A method and system for enhanced bus access in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously. In response to one or more pending transactions, each processor outputs a request to bus arbitration logic for a maximum-permitted number of sub-buses. If the number of sub-buses granted to a particular processor equals the number of pending transactions at that processor, all pending transactions are performed in parallel on separate sub-buses. If the number of sub-buses granted is less than the number of pending transactions, pending transactions are performed in a priority order.

Abstract: A method and system for enhanced bus arbitration in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously. In response to one or more pending transactions, each processor outputs a request to bus arbitration logic for a number of sub-buses. A maximum number of sub-buses is specified for each processor and the processors are prioritized. Each time a bus request is received from a processor, the number of requested sub-buses is granted, if that number is equal to or less than the specified maximum number of sub-buses for that processor. If the requested number of sub-buses is greater than the specified maximum number of sub-buses for that processor the requested number is granted if no other processor has issued a bus request.

Abstract: A computer system is provided, comprising system memory and a memory controller which resides on a system bus for controlling access to the system memory, a bus interface unit and a direct memory access controller also residing on the system bus, and a central processing unit electrically connected with the memory controller which is able to read and write data to the system memory via the memory controller. The memory controller and the bus interface unit each operate, when either is in control of the system bus, at a clock frequency which is a multiple of the clock frequency at which the direct memory access controller operates on the system bus. The memory controller and the bus interface unit each operate, when the direct memory access controller is in control of the system bus, at the same clock frequency as that of the direct memory access controller. The clock frequencies of the memory controller, the bus interface unit and the direct memory access controller are each synchronized in time.