Patents by Inventor Carissima Marie Hudson

Carissima Marie Hudson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10781532
    Abstract: Methods for forming single crystal silicon ingots with improved resistivity control. The methods involve growth and resistivity measurement of a sample rod. The sample rod may have a diameter less than the diameter of the product ingot. The resistivity of the sample rod may be measured directly by contacting a resistivity probe with a planar segment formed on the sample rod. The sample rod may be annealed in a thermal donor kill cycle prior to measuring the resistivity.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: September 22, 2020
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Carissima Marie Hudson, JaeWoo Ryu, Richard J. Phillips, Robert Standley, HyungMin Lee, YoungJung Lee
  • Publication number: 20200216975
    Abstract: A method for preparing a single crystal silicon ingot and a wafer sliced therefrom are provided. The ingots and wafers comprise nitrogen at a concentration of at least about 1×1014 atoms/cm3 and/or germanium at a concentration of at least about 1×1019 atoms/cm3, interstitial oxygen at a concentration of less than about 6 ppma, and a resistivity of at least about 1000 ohm cm.
    Type: Application
    Filed: June 6, 2017
    Publication date: July 9, 2020
    Inventors: Soubir Basak, Igor Peidous, Carissima Marie Hudson, HyungMin Lee, ByungChun Kim, Robert J. Falster
  • Patent number: 10707093
    Abstract: The disclosure is directed to a method to recover the gate oxide integrity yield of a silicon wafer after rapid thermal anneal in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2. Generally, rapid thermal anneals in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2 to thereby imprint an oxygen precipitate profile can degrade the GOI yield of a silicon wafer by exposing as-grown crystal defects (oxygen precipitate) and vacancies generated by the silicon nitride film. The present invention restores GOI yield by stripping the silicon nitride layer, which is followed by wafer oxidation, which is followed by stripping the silicon oxide layer.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: July 7, 2020
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Young Jung Lee, Jae-Woo Ryu, Byung Chun Kim, Robert J. Falster, Soon Sung Park, Tae Hoon Kim, Jun Hwan Ji, Carissima Marie Hudson
  • Publication number: 20200208294
    Abstract: Methods for forming single crystal silicon ingots with improved resistivity control are disclosed. The methods involve growth of a sample rod. The sample rod may have a diameter less than the diameter of the product ingot. The sample rod is cropped to form a center slab. The resistivity of the center slab may be measured directly such as by a four-point probe. The sample rod or optionally the center slab may be annealed in a thermal donor kill cycle prior to measuring the resistivity, and the annealed rod or slab is irradiated with light in order to enhance the relaxation rate and enable more rapid resistivity measurement.
    Type: Application
    Filed: December 11, 2019
    Publication date: July 2, 2020
    Inventors: Carissima Marie Hudson, HyungMin Lee, JaeWoo Ryu, Richard J. Phillips, Robert Wendell Standley
  • Publication number: 20200199774
    Abstract: Methods for forming single crystal silicon ingots with improved resistivity control are disclosed. The methods involve growth of a sample rod. The sample rod may have a diameter less than the diameter of the product ingot. The sample rod is cropped to form a center slab. The resistivity of the center slab may be measured directly such as by a four-point probe. The sample rod may be annealed in a thermal donor kill cycle prior to measuring the resistivity.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Inventors: HyungMin Lee, JaeWoo Ryu, Richard Phillips, YoungJung Lee, Carissima Marie Hudson
  • Publication number: 20200199773
    Abstract: Methods for forming single crystal silicon ingots with improved resistivity control are disclosed. The methods involve growth of a sample rod. The sample rod may have a diameter less than the diameter of the product ingot. The sample rod is cropped to form a center slab. The resistivity of the center slab may be measured directly such as by a four-point probe. The sample rod may be annealed in a thermal donor kill cycle prior to measuring the resistivity.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Inventors: HyungMin Lee, JaeWoo Ryu, Richard Phillips, YoungJung Lee, Carissima Marie Hudson
  • Publication number: 20200199775
    Abstract: Methods for forming single crystal silicon ingots with improved resistivity control are disclosed. The methods involve growth of a sample rod. The sample rod may have a diameter less than the diameter of the product ingot. The sample rod is cropped to form a center slab. The resistivity of the center slab may be measured directly such as by a four-point probe. The sample rod may be annealed in a thermal donor kill cycle prior to measuring the resistivity.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Inventors: HyungMin Lee, JaeWoo Ryu, Richard Phillips, YoungJung Lee, Carissima Marie Hudson
  • Publication number: 20200002843
    Abstract: Methods for forming single crystal silicon ingots in which plural sample rods are grown from the melt are disclosed. A parameter related to the impurity concentration of the melt or ingot is measured. In some embodiments, the sample rods each have a diameter less than the diameter of the product ingot.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: Carissima Marie Hudson, JaeWoo Ryu
  • Publication number: 20200002835
    Abstract: Methods for forming single crystal silicon ingots with improved resistivity control. The methods involve growth and resistivity measurement of a sample rod. The sample rod may have a diameter less than the diameter of the product ingot. The resistivity of the sample rod may be measured directly by contacting a resistivity probe with a planar segment formed on the sample rod. The sample rod may be annealed in a thermal donor kill cycle prior to measuring the resistivity.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: Carissima Marie Hudson, JaeWoo Ryu, Richard J. Phillips, Robert Standley, HyungMin Lee, YoungJung Lee
  • Publication number: 20200002836
    Abstract: Methods for forming single crystal silicon ingots with improved resistivity control. The methods involve growth and resistivity measurement of a sample rod. The sample rod may have a diameter less than the diameter of the product ingot. The resistivity of the sample rod may be measured directly by contacting a resistivity probe with a planar segment formed on the sample rod. The sample rod may be annealed in a thermal donor kill cycle prior to measuring the resistivity.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: Carissima Marie Hudson, JaeWoo Ryu, Richard J. Phillips, Robert Standley, HyungMin Lee, YoungJung Lee
  • Publication number: 20200002837
    Abstract: Methods for forming single crystal silicon ingots in which plural sample rods are grown from the melt are disclosed. A parameter related to the impurity concentration of the melt or ingot is measured. In some embodiments, the sample rods each have a diameter less than the diameter of the product ingot.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: Carissima Marie Hudson, JaeWoo Ryu
  • Patent number: 10513796
    Abstract: An method for producing a silicon ingot includes melting polycrystalline silicon in a crucible enclosed in a vacuum chamber to form a melt, generating a cusped magnetic field within the vacuum chamber, dipping a seed crystal into the melt, withdrawing the seed crystal from the melt to pull a single crystal that forms the silicon ingot, wherein the silicon ingot has a diameter greater than about 150 millimeters (mm), and simultaneously regulating a plurality of process parameters such that the silicon ingot has an oxygen concentration less than about 5 parts per million atoms (ppma). The plurality of process parameters include a wall temperature of the crucible, a transport of silicon monoxide (SiO) from the crucible to the single crystal, and an evaporation rate of SiO from the melt.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: December 24, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Soubir Basak, Carissima Marie Hudson, Gaurab Samanta, Jae-Woo Ryu, Hariprasad Sreedharamurthy, Kirk D. McCallum, HyungMin Lee
  • Patent number: 10453703
    Abstract: The disclosure is directed to a method to recover the gate oxide integrity yield of a silicon wafer after rapid thermal anneal in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2. Generally, rapid thermal anneals in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2 to thereby imprint an oxygen precipitate profile can degrade the GOI yield of a silicon wafer by exposing as-grown crystal defects (oxygen precipitate) and vacancies generated by the silicon nitride film. The present invention restores GOI yield by stripping the silicon nitride layer, which is followed by wafer oxidation, which is followed by stripping the silicon oxide layer.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: October 22, 2019
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Young Jung Lee, Jae-Woo Ryu, Byung Chun Kim, Robert J. Falster, Soon Sung Park, Tae Hoon Kim, Jun Hwan Ji, Carissima Marie Hudson
  • Publication number: 20190267251
    Abstract: The disclosure is directed to a method to recover the gate oxide integrity yield of a silicon wafer after rapid thermal anneal in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2. Generally, rapid thermal anneals in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2 to thereby imprint an oxygen precipitate profile can degrade the GOI yield of a silicon wafer by exposing as-grown crystal defects (oxygen precipitate) and vacancies generated by the silicon nitride film. The present invention restores GOI yield by stripping the silicon nitride layer, which is followed by wafer oxidation, which is followed by stripping the silicon oxide layer.
    Type: Application
    Filed: May 9, 2019
    Publication date: August 29, 2019
    Inventors: Young Jung Lee, Jae-Woo Ryu, Byung Chun Kim, Robert J. Falster, Soon Sung Park, Tae Hoon Kim, Jun Hwan Ji, Carissima Marie Hudson
  • Publication number: 20190153615
    Abstract: Systems and methods for forming an ingot from a melt are disclosed. A method includes placing conditioning members within a cavity defined by a crucible and placing feedstock material into the cavity. The method also includes melting the feedstock material to form the melt. A melt line is defined by a surface of the melt. The conditioning members including quartz bodies arranged at the melt line to contact the melt and reduce the number of micro-voids in the melt.
    Type: Application
    Filed: January 17, 2019
    Publication date: May 23, 2019
    Inventors: Salvador Zepeda, Richard J. Phillips, Christopher Vaughn Luers, Steven Lawrence Kimbel, Harold W. Korb, John D. Holder, Carissima Marie Hudson, Hariprasad Sreedharamurthy, Stephan Haringer, Marco Zardoni
  • Patent number: 10221500
    Abstract: Systems and methods for forming an ingot from a melt are disclosed. A system includes a crucible defining a cavity for receiving the melt, and a first and second barrier to inhibit movement of the melt. A first passageway and a second passageway are arranged to allow the melt located within an outer zone to move into and through a transition zone and into an inner zone. Conditioning members are placed in at least one of the zones and arranged to contact the melt to reduce the number of micro-voids in the melt.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: March 5, 2019
    Assignee: Corner Star Limited
    Inventors: Salvador Zepeda, Richard J. Phillips, Christopher Vaughn Luers, Steven Lawrence Kimbel, Harold W. Korb, John D. Holder, Carissima Marie Hudson, Hariprasad Sreedharamurthy, Stephan Haringer, Marco Zardoni
  • Publication number: 20180291524
    Abstract: Methods for growing single crystal ingots doped with volatile dopants and ingots grown according to the methods are described herein.
    Type: Application
    Filed: April 29, 2016
    Publication date: October 11, 2018
    Inventors: Soubir Basak, Gaurab Samanta, Salvador Zepeda, Christopher V. Luers, Steven L. Kimbel, Carissima Marie Hudson, Hariprasad Sreedharamurthy, Roberto Scala, Richard J. Phillips, Tirumani N. Swaminathan, Jihong Chen, Stephen Wayne Palmore, Peter Drury Wildes
  • Publication number: 20180237938
    Abstract: An method for producing a silicon ingot includes melting polycrystalline silicon in a crucible enclosed in a vacuum chamber to form a melt, generating a cusped magnetic field within the vacuum chamber, dipping a seed crystal into the melt, withdrawing the seed crystal from the melt to pull a single crystal that forms the silicon ingot, wherein the silicon ingot has a diameter greater than about 150 millimeters (mm), and simultaneously regulating a plurality of process parameters such that the silicon ingot has an oxygen concentration less than about 5 parts per million atoms (ppma). The plurality of process parameters include a wall temperature of the crucible, a transport of silicon monoxide (SiO) from the crucible to the single crystal, and an evaporation rate of SiO from the melt.
    Type: Application
    Filed: April 23, 2018
    Publication date: August 23, 2018
    Inventors: Soubir Basak, Carissima Marie Hudson, Gaurab Samanta, Jae-Woo Ryu, Hariprasad Sreedharamurthy, Kirk D. McCallum, HyungMin Lee
  • Publication number: 20180187329
    Abstract: Systems and methods for forming an ingot from a melt are disclosed. A system includes a crucible defining a cavity for receiving the melt, and a first and second barrier to inhibit movement of the melt. A first passageway and a second passageway are arranged to allow the melt located within an outer zone to move into and through a transition zone and into an inner zone. Conditioning members are placed in at least one of the zones and arranged to contact the melt to reduce the number of micro-voids in the melt.
    Type: Application
    Filed: January 4, 2017
    Publication date: July 5, 2018
    Inventors: Salvador Zepeda, Richard J. Phillips, Christopher Vaughn Luers, Steven Lawrence Kimbel, Harold W. Korb, John D. Holder, Carissima Marie Hudson, Hariprasad Sreedharamurthy, Stephan Haringer, Marco Zardoni
  • Publication number: 20180182641
    Abstract: The disclosure is directed to a method to recover the gate oxide integrity yield of a silicon wafer after rapid thermal anneal in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2. Generally, rapid thermal anneals in an ambient atmosphere comprising a nitrogen containing gas, such as NH3 or N2 to thereby imprint an oxygen precipitate profile can degrade the GOI yield of a silicon wafer by exposing as-grown crystal defects (oxygen precipitate) and vacancies generated by the silicon nitride film. The present invention restores GOI yield by stripping the silicon nitride layer, which is followed by wafer oxidation, which is followed by stripping the silicon oxide layer.
    Type: Application
    Filed: December 13, 2017
    Publication date: June 28, 2018
    Inventors: Young Jung Lee, Jae-Woo Ryu, Byung Chun Kim, Robert Falster, Soon Sung Park, Tae Hoon Kim, Jun Hawn Ji, Carissima Marie Hudson