Patents by Inventor Carl Alelyunas
Carl Alelyunas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210036905Abstract: In one embodiment, an apparatus includes first and second tuners to receive and process a radio frequency (RF) signal and output a first and second plurality of frequency domain sub-carriers. The apparatus may further include a combiner circuit to combine a first plurality of demodulated frequency domain sub-carriers and a second plurality of demodulated frequency domain sub-carriers into a plurality of combined frequency domain sub-carriers, and an output circuit coupled to the combiner circuit. In a first mode, the output circuit is to embed a format indicator with each of the plurality of combined frequency domain sub-carriers to indicate a frequency domain format, and to output the plurality of combined frequency domain sub-carriers with the embedded format indicator to a downstream processing circuit for channel decoding.Type: ApplicationFiled: July 31, 2019Publication date: February 4, 2021Inventors: Ken Strickland, Bradley Arthur Wallace, Carl Alelyunas, Vladimir Mesarovic
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Patent number: 10911289Abstract: In one embodiment, an apparatus includes first and second tuners to receive and process a radio frequency (RF) signal and output a first and second plurality of frequency domain sub-carriers. The apparatus may further include a combiner circuit to combine a first plurality of demodulated frequency domain sub-carriers and a second plurality of demodulated frequency domain sub-carriers into a plurality of combined frequency domain sub-carriers, and an output circuit coupled to the combiner circuit. In a first mode, the output circuit is to embed a format indicator with each of the plurality of combined frequency domain sub-carriers to indicate a frequency domain format, and to output the plurality of combined frequency domain sub-carriers with the embedded format indicator to a downstream processing circuit for channel decoding.Type: GrantFiled: July 31, 2019Date of Patent: February 2, 2021Assignee: SILICON LABORATORIES INC.Inventors: Ken Strickland, Bradley Arthur Wallace, Carl Alelyunas, Vladimir Mesarovic
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Patent number: 8965135Abstract: A system for cadence break detection is provided. The system includes a field system receiving a plurality of fields of image data. A threshold system generates a cadence break signal if a difference in two fields exceeds a predetermined threshold. A sequence system generates the cadence break signal if a sequence of differences between the plurality of fields does not match a predetermined sequence.Type: GrantFiled: March 19, 2008Date of Patent: February 24, 2015Assignee: Conexant Systems, Inc.Inventor: Carl Alelyunas
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Patent number: 8396322Abstract: Methods for reducing optical distortion such as keystone distortion can include receiving an input image and modifying the input image by applying two separate 1D operations to the input image and applying a polyphase filter to the input image, where the first 1D operation is performed after application of the second 1D operation has begun. The modified image can then be projected.Type: GrantFiled: June 11, 2008Date of Patent: March 12, 2013Assignee: Pixelworks, Inc.Inventors: Neil D. Woodall, Carl Alelyunas, Minghui Yang
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Publication number: 20090238471Abstract: A system for cadence break detection is provided. The system includes a field system receiving a plurality of fields of image data. A threshold system generates a cadence break signal if a difference in two fields exceeds a predetermined threshold. A sequence system generates the cadence break signal if a sequence of differences between the plurality of fields does not match a predetermined sequence.Type: ApplicationFiled: March 19, 2008Publication date: September 24, 2009Inventor: Carl Alelyunas
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Patent number: 7072999Abstract: A robust packet arrival time detector using a power estimate to validate a packet arrival time measurement. A packet arrival time measurement is considered valid when the value of the power estimate signal indicates that a packet is being received. A power estimator comprises a bandpass filter, a Hilbert transform, two squaring devices, an adder, and a lowpass filter.Type: GrantFiled: June 26, 2001Date of Patent: July 4, 2006Assignee: 2Wire, Inc.Inventors: Philip DesJardins, Scott A. Lery, Carl Alelyunas
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Patent number: 7072385Abstract: Systems and methods are disclosed for improving DSL performance, including ADSL and VDSL performance, over a local loop between a telephone company central office and a customer premises. In particular, a DSL repeater is coupled to the local loop and amplifies downstream and upstream DSL signals to at least partially compensate for DSL signal attenuation that occurs as DSL signals pass over the local loop. Pursuant to one embodiment, the DSL repeater includes a POTS load coil to improve the POTS, or voice band, transmission over the local loop. According to this embodiment, the DSL repeater provides both improved POTS band signal transmission and DSL service. One embodiment of the load coil includes a coupled inductor having compensating capacitors coupled thereto for counter-balancing the inter-winding capacitance of the coupled inductor. In another embodiment, the load coil includes a high intra-winding capacitance for counter-balancing the inter-winding capacitance of a coupled inductor.Type: GrantFiled: September 26, 2000Date of Patent: July 4, 2006Assignee: 2Wire, Inc.Inventors: Brian L. Hinman, Andrew L. Norrell, James Schley-May, Carl Alelyunas
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Patent number: 6542028Abstract: An efficient demodulation and low pass filter structure comprises a shift-add-negate structure that effectively multiplies each received sample by a combined demodulation and filter coefficient, and an accumulator that accumulates the products. Low pass filter coefficients are selected such that the shift-add-negate structure implements multiplications by shifts, adds, and negations. In the preferred embodiment, the demodulation and low pass filter structure outputs three complex samples per symbol.Type: GrantFiled: July 27, 2001Date of Patent: April 1, 2003Assignee: 2Wire, Inc.Inventors: Andrew L. Norrell, Philip DesJardins, Carl Alelyunas
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Patent number: 6038430Abstract: A method and apparatus are provided that improve data transmissions in a wireless network, optimized for the transmissions of voice signals, by companding data signals electrically about a spectral shaping module in data handling devices, preferably modems, at both the transmitting and receiving ends of the wireless network. At the transmitting end, the companding is performed by a compressor, electrically preceding a data de-emphasis module, and an expander, electrically succeeding the data de-emphasis module. At the receiving end, the companding is performed by a compressor, electrically preceding a data pre-emphasis module, and an expander, electrically succeeding the data pre-emphasis module.Type: GrantFiled: December 10, 1997Date of Patent: March 14, 2000Assignee: 3Com CorporationInventors: Larry Steve Thomson, Carl Alelyunas, Bert Buxton
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Patent number: 5528308Abstract: Direct synthesis of a digital audio sample clock from a digital video sample clock is achieved by using a numerically controlled oscillator driven by the digital video sample clock. A phase accumulator increments a phase increment at the frequency of the digital video sample clock, the phase increment being a function of a desired frequency for the digital audio sample clock, the frequency of the digital video sample clock and the bit precision of the accumulator. The accumulated phase output from the accumulator is converted into a sine wave signal at the desired audio frequency from which the digital audio sample clock is derived.Type: GrantFiled: May 31, 1994Date of Patent: June 18, 1996Assignee: The Grass Valley Group, Inc.Inventors: Carl Alelyunas, Michael Poimboeuf
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Patent number: 5406309Abstract: A display memory and controller for displaying waveforms and vectors on raster-scanned conventional video monitors so that the display appears the same as oscilloscope or monitor displays. The brightness of any spot is set by the number of times that an input signal is at the same position on repetitive equivalent sweeps. As the signal passes a time and voltage point, the memory is read to determine the brightness level from before, and a new level is written in to approximate the intensity function of CRT phosphor. As the memory is displayed, the values are decreased to approximate the decay of a CRT phosphor. A memory controller allows the signal to be directly input to memory for later processing for fault determination.Type: GrantFiled: February 26, 1993Date of Patent: April 11, 1995Assignee: Magni Systems, Inc.Inventor: Carl Alelyunas
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Patent number: 5321424Abstract: A graticule display processor that can produce an adaptive graticule for a raster-scan output waveform monitor. The graticule may be displayed in front of the waveform, behind the waveform or mixed with the waveform. The graticule can change the waveform's color or intensity in specific regions, thereby enhancing the appearance of over range conditions. A specific use is to allow the vector functions of phase and gain to be monitored in the waveform mode.Type: GrantFiled: December 11, 1992Date of Patent: June 14, 1994Assignee: Magni Systems, Inc.Inventor: Carl Alelyunas