Abstract: A disk drive having an embedded servo disk format preferably having a fixed-number of radial servo sample wedges per track, in which data blocks are located independently of the servo sample wedge locations of any particular track, and can be split around servo sample wedges. Thus, a fraction of a data block, or more than one data block, can be written between consecutive servo sample wedges, beginning almost anywhere in a data wedge. Each data sector has an associated identification (ID) field that includes at least one segment descriptor. Each segment descriptor describes the data segments into which a data block can be split. Provision is made for as many segment descriptors as there can be data segments for a data block. In general, a segment descriptor is a multi-bit digital signal that defines the absolute or relative location of split data segments (or, alternatively, the absolute or relative length of split data segments, from which the location can be determined).

Abstract: A disk drive having error detection and correction capability includes a dedicated finite field processor for performing corrections and for generating software syndromes for miscorrection detection. The processor operates over a finite field under program control and performs parallel finite field multiplication and addition operations in a single execution cycle.

Abstract: An intelligent disk drive employing a controller which performs high speed error correction and miscorrection detection using a finite field processor. The error correction code is defined over a finite field and the error detection code is defined over an extension field of the finite field. The finite field processor performs calculation over both the finite field and extension field to provide high speed error correction and correction validation.

Abstract: An intelligent disk drive having error detection and correction capability employs an embedded error correction controller with a pipelined architecture for performing error correction under program control. The pipelined architecture provides parallel operand fetching and instruction execution for high speed operations during error correction.

Abstract: An intelligent disk drive includes a controller which embeds user data address information into error correction code check symbols written to the data storage disk. The address information is not written to disk, but address errors are detected by decoding the error correction code check symbols during read operations. Disk space is saved while maintaining robust address error detection.

Abstract: A circuit is provided for control and data transfer between a standard data storage device interface and one of a choice of several host computers. Parallel transition memories in conjunction with a buffer memory under common control of a buffer manager increase the transfer efficiency between the data storage unit and the host computer. Selectable register banks provide interface compatibility with multiple host computers for implementation of the invention.

Abstract: The invention provides a method and circuit for control of intelligent or integrated disk drives whereby a single computer address port may be used for control of two intelligent disk drives. The circuit requires only a single jumper connection for definition of the drive address. Tristate drivers on all output circuits from the disk drive controller to the host computer are disabled when the drive is not selected.

Abstract: The invention provides a method and architecture for reading data from a track on a data disk with no latency in initiation of the data transfer due to sector alignment. Sector identification bytes are compared for track identification while sector number is written for storage in a table lookup with a buffer address for storage of the data.

Abstract: The invention provides a method and format for storing a relocation identification block within the data field of a sector having a defect. The relocation identification block provides an address for a replacement sector to be used for data which cannot be stored in the unusable sector.

Abstract: The invention provides a circuit for selecting a first clock, disabling a second or additional clocks and positively enabling the selected first clock only after the second or additional clocks no longer provide signal to the circuit.

Abstract: The invention provides a circuit for use with a standard bidirectional databus having an active current device providing a first logic level in combination with a selectably jumpered passive resistance device providing a second logic level, the active element responsive to an enable signal whereby tristating the bus write drivers and reading the bus will sense a configuration determined by selection of the jumper.