Abstract: A System on Chip (SoC) includes a first core coupled to an interconnect; a second core coupled to the interconnect; a memory coupled to the interconnect and including a plurality of evenly sized partitions; and storage circuitry configured to store memory configuration information. The memory configuration information defines a memory configuration and is configured to indicate a series of swappable segments for each core of the SoC by indicating, for each core, a first number of partitions of the memory assigned to each of a first swappable segment and a second swappable segment for the core, the first swappable segment designated as an active segment and the second swappable segment designated as a first backup segment, and an enable indicator to indicate whether or not to assign the first number of partitions to a third swappable segment designated as a second backup segment.

Abstract: A processing system including processors, peripheral slots, hardware resources, and gateway circuitry. Each processor is assigned a corresponding identifier. The peripheral slots are located within an addressable peripheral space. Each hardware resource is placed into a corresponding peripheral slot, including at least one direct memory access (DMA) device supporting at least one DMA channel and at least one general-purpose input/output (GPIO) pin. Memory protection and gateway circuitry is programmed to control access of the hardware resources only by a processor that provides a matching identifier. The memories along with hardware resources are protected against unauthorized accesses to isolate applications executed on each processor within a multicore system and hence support freedom of interference.

Abstract: A processing system including processors, peripheral slots, hardware resources, and gateway circuitry. Each processor is assigned a corresponding identifier. The peripheral slots are located within an addressable peripheral space. Each hardware resource is placed into a corresponding peripheral slot, including at least one direct memory access (DMA) device supporting at least one DMA channel and at least one general-purpose input/output (GPIO) pin. Memory protection and gateway circuitry is programmed to control access of the hardware resources only by a processor that provides a matching identifier. The memories along with hardware resources are protected against unauthorized accesses to isolate applications executed on each processor within a multicore system and hence support freedom of interference.

Abstract: A mechanism for making multiple security schemes available in a single embedded system without requiring a firmware update or a hardware extension is provided. Embodiments provide firmware support for storing parameters related to each available security scheme and a selection mechanism to select the desired security scheme for the application utilizing the embedded system. Embodiments can also provide a status register to provide to a user an identification of the security scheme that is presently enabled on the embedded system. Embodiments can further prevent a malicious user from selecting an invalid security scheme.

Abstract: An electronic device, typically a microcontroller, which is divided into a multiplicity of power domains comprising one or more intelligent peripherals, is provided with an on-board power management module for switching power to one or more domains for pre-determined time periods and in a predetermined sequence. The values of the predetermined time periods and sequence may be pre-programmed by the design engineer or user of the device. In one example, power is switched to domains in a round robin fashion. An optional interrupt capability permits selective application of power to a dormant intelligent peripheral requesting it at the expense of others and based on a priority scheme. Consumption of current supplied to power domains may be monitored by a power watchdog or alternatively via a dedicated power monitor associated with each intelligent peripheral. The invention helps to reduce device power consumption without any associated reduction in processing performance.

Abstract: A circuit includes a first external terminal, a first lower resolution analog-to-digital converter (LRADC) coupled to the external terminal and configured to perform a first conversion of an analog signal received at the external terminal to a digital value, and a higher resolution analog-to-digital converter (HRADC). The HRADC is configured to selectively receive the analog signal from the first external terminal based on the digital value. When the digital value outputted by the first LRADC indicates a change in value of the received analog signal, the HRADC is provided with the analog signal and performs a second conversion of the analog signal to a second digital value. The first LRADC has a lower conversion resolution as compared to the HRADC.

Abstract: A comparator circuit includes a first transistor have a control electrode coupled to a first input voltage, a first current electrode coupled to a second input voltage, and a second current electrode coupled to a first circuit node. The circuit also includes a first inverter coupled to a first voltage supply terminal and having a first input coupled to the first circuit node and an output, a second transistor having a control electrode coupled to the output of the first inverter, and an active resistive element coupled in series between the first circuit node and a first current electrode of the second transistor.

Abstract: A comparator circuit includes a first transistor have a control electrode coupled to a first input voltage, a first current electrode coupled to a second input voltage, and a second current electrode coupled to a first circuit node. The circuit also includes a first inverter coupled to a first voltage supply terminal and having a first input coupled to the first circuit node and an output, a second transistor having a control electrode coupled to the output of the first inverter, and an active resistive element coupled in series between the first circuit node and a first current electrode of the second transistor.

Abstract: An electronic device includes a plurality of modules coupled to a charge storage node. A method for operating the electronic device includes starting up the electronic device and entering a demonstration mode. During the demonstration mode, a demonstration is performed for a predetermined amount of time by enabling a subset of the plurality of modules. At the expiration of the predetermined amount of time, the electronic device is shut down. If the electronic device is operating in normal operating mode, the charge level of the charge storage cell can be monitored such that when it falls below a minimum charge threshold, the electronic device is shut down. The minimum charge threshold can be based on a number of demonstrations to be performed on a remaining capacity of the charge storage cell.

Abstract: A micro controller unit including an error indicator hardware module, the error indicator module being arranged to respond to event signals representative of internal and external fault and error events perturbing the micro controller unit function by registering in non-volatile memory a record of the nature of each of the events, wherein the record of the events is inaccessible to alteration.

Abstract: A method of controlling access by a master to a peripheral includes receiving an interrupt priority level from an interrupt controller associated with the peripheral, comparing the interrupt priority level with respective a pre-established interrupt access level to obtain an interrupt level comparison result, establishing whether an access condition is satisfied in dependence on the interrupt level comparison result, and if the access condition is satisfied, granting access. If the access condition is not satisfied, access is denied. Further, a circuitry is described including a master, a peripheral, and an access control circuitry including an interrupt controller associated with the peripheral. The access control circuitry is arranged to perform a method of controlling access by the master to the peripheral.

Abstract: A method of controlling direct memory access of a peripheral memory of a peripheral by a master is described. The method includes checking whether there is a pending request from the peripheral for a direct memory access service, establishing whether an access condition is satisfied in dependence on at least whether there is a pending request, and, if the access condition is satisfied, granting access to the master. Also, an associated device and an associated computer program product are described.

Abstract: A reset state control circuit adapted to reset independent device domains of an electronic device, said reset state control circuit comprising a capturing unit adapted to capture reset events; and a reset shaping logic adapted to change dynamically a reset control flow to reset device domains of said electronic device depending on a sequence of the reset events captured by said capturing unit.

Abstract: A built-in self test system comprises an integrated circuit device comprising a plurality of functional units coupled to built-in self test circuitry; a low power control unit operable to switch the integrated circuit device into a low power mode and to generate a BIST wake-up signal during or before entering the low power mode; and a built-in self test control unit coupled to the built-in self test circuitry and the low power control unit and arranged to initiate a built-in self test when receiving the BIST wake-up signal.

Abstract: An I/O cell comprising a first set of driver stages comprising, each driver stage of the first set comprising a high side switch controllable to couple an I/O node of the I/O cell to a first high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a first low voltage supply node. The I/O cell further comprising a second set of driver stages, each driver stage of the second set comprising a high side switch controllable to couple the I/O node of the I/O cell to a second high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a second low voltage supply node. The switches of the first set of driver stages are controllable independently of the switches of the second set of driver stages.

Abstract: A microprocessor comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event, determine if at least one reset condition has been met upon detection of the reset event, and cause at least a part of the microprocessor to remain in a reset state upon determining that the at least one reset condition has been met.

Abstract: Systems and methods for managing cold-crank events. In an embodiment, a method may include detecting a cold-crank event and setting a switching circuit to a non-conductive state, where the switching circuit is configured to couple a first regulator to a memory circuit such that setting the switching circuit to the non-conductive state de-couples the memory circuit from the first regulator. The method may also include setting the switching circuit to a conductive state in current limitation mode during a recovery period following the cold-crank event to re-couple the memory circuit to the first regulator. In another embodiment, an electronic device include a switching circuit, a first regulator coupled to a first terminal of the switching circuit, a second regulator coupled to a second terminal of the switching circuit, a logic circuit coupled to the switching circuit, and a memory circuit coupled to the second terminal of the switching circuit.

Abstract: An electronic device includes a plurality of modules coupled to a charge storage node. A method for operating the electronic device includes starting up the electronic device and entering a demonstration mode. During the demonstration mode, a demonstration is performed for a predetermined amount of time by enabling a subset of the plurality of modules. At the expiration of the predetermined amount of time, the electronic device is shut down. If the electronic device is operating in normal operating mode, the charge level of the charge storage cell can be monitored such that when it falls below a minimum charge threshold, the electronic device is shut down. The minimum charge threshold can be based on a number of demonstrations to be performed on a remaining capacity of the charge storage cell.

Abstract: A mode-controlled voltage excursion detector apparatus for monitoring a supply voltage of a power supply applied to a load and a method of operating thereof is described. A voltage monitor is configured to detect an excursion event if the supply voltage exceeds or falls below at least one defined threshold, to generate an excursion event signal upon detection of the excursion event and to provide the generated excursion event signal to the excursion event output for being outputted via an excursion event output. A sensitivity control module is configured to receive a signal indicative of potential voltage excursions. A sensitivity control module is further operatively coupled to the sensitivity control input and configured to disable the outputting of an excursion event signal generated during a defined period of time in response to the reception of the signal, which triggers the disabling of the outputting.

Abstract: A microprocessor device comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event comprising a first reset level, determine if at least one reset condition has been met upon detection of the reset event comprising the first reset level, and cause a reset of a second reset level upon determining that the at least one reset condition has been met.