Abstract: A data storage subsystem which reduces seek time, by defining a logical storage space wherein part of the logical storage space is defined to correspond to a primary storage space of a first physical data storage device, and correspond to a secondary storage space of a second physical data storage device, and another part of the logical storage space is defined to correspond to a primary storage space of the second physical data storage device, and correspond to a secondary storage space of the first physical data storage device. For hard disk drives having an arm assembly with a read/write head, the average seek distance for both drives reduced, since the pivoting arm assembly need not travel as far to reach each physical storage address within a primary storage area. The invention may additionally take advantage of geometric or other aspects of the storage devices which result in some portion of the device having a faster access time that another portion.

Abstract: Disclosed is a bridge system for processing read and write transactions over a bus in which in a preferred embodiment continuous read data obtained from a target device in a number of separate read operations over a secondary bus may be gathered by the bridge and assembled into a larger block of data before forwarding the data over the primary bus to the requesting agent. As a consequence, the transmission of optimal, address boundary-aligned bursts of read data over the primary bus may be increased and conversely, the transmission of fractionated, nonaligned read data over the primary bus may be reduced. Because each agent is assigned particular buffers, read data may be gathered concurrently in the assigned bridge buffers without assertion of a read request by one agent causing the flushing of the data being gathered for a different agent.

Abstract: An improved multi-bit error correction system. The inventive error correcting system performs a fast error correction operation on individual bits within multi-bit modules. In a specific implementation, the invention uses Hamming codes and divides an n times m bit data word into m modules, with each module having n bits. Next, the ith bits of each module are combined to form a set of parity bits. Syndrome bits are generated from the parity bits and used to locate errors in the bits and provide an indication of same. Finally, errors in the bits are corrected in a conventional manner to provide corrected data bits.

Abstract: A trace facility for a computer system attachment network, a method for operating that network, and trace tools in the network. The network has a plurality of the trace tools, each connected to a communication path, the trace facility providing a system wide trace. The trace facility comprises at least one trace buffer at each trace tool. Each trace tool has an address filter selecting an address range of information on the bus, the information being communicated on the bus as events, and storing the selected event information in the trace buffers, thereby conducting a trace. A breakpoint connection is provided interconnecting each of the trace tools. A trace tool control at each trace tool responds to a trace stop command addressed to the trace tool, to stop the trace at its address filter and trace buffer, and to issue a breakpoint signal on the breakpoint connection to all the interconnected trace tools.

Abstract: Disclosed is a system for handling errors. A system managed by a processor processes an error in the system. The system then generates an interrupt to the processor indicating that an error occurred and executes an error mode before the processor interprets the interrupt. As part of the error mode, the system prevents data from transferring between the system and the processor and processes a read request from the processor to the system by returning data to the processor unrelated to the requested data. The processor would then process the interrupt indicating the error and execute a diagnostic mode to diagnose the error in the system.

Abstract: Disclosed is a system for communication among a device, a first processor, and a second processor. One of a first data path and second data path is configured. The first data path comprises a bus, such as a local PCI bus, a first remote bridge, and a first local bridge. The bridges may be comprised of PCI to PCI bridges. After configuring the first data path, the device communicates to the first processor by communicating data through the bus to the first remote bridge. The first remote bridge transmits the data to the first local bridge and the first local bridge transmits the data to the first processor. The second data path comprises the bus, a second remote bridge, and a second local bridge. After configuring the second data path, the device communicates to the second processor by communicating data through the bus to the second remote bridge. The second remote bridge transmits the data to the second local bridge and the second local bridge transmits the data to the second processor.