Patents by Inventor Carl H. Fong

Carl H. Fong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6357036
    Abstract: The present invention provides a bond tool utility software package which extracts bond pad location data from a semiconductor chip design stored in one of a number of known formats (e.g., Opus, GDSII, or the like) and extracts conductor location data from an AUTOCAD file of a chip frame design. The utility retrieves bonding connection data from a design ASCII file and generates a bonding diagram for the semiconductor assembly. The utility also contains a subroutine for applying bonding design criteria to the resultant bonding diagram to determine whether all bonds are within established guidelines. If an impermissible bond is formed, the user may be alerted that one or more bonding pads may have to be relocated. In one embodiment of the present invention, the bonding utility may interface with a semiconductor design circuit to generate a suggested fix to an impermissible bonding situation. One or more bonding pads may be moved in the semiconductor design to correct for potential bonding deficiencies.
    Type: Grant
    Filed: April 29, 1999
    Date of Patent: March 12, 2002
    Assignee: Cirrus Logic, Inc.
    Inventors: Laiman Eka, Marcello R. Martinez, III, Carl H. Fong
  • Patent number: 6256549
    Abstract: The present invention provides a computerized database comprising a first table representing a list of part numbers. The database provides computerized links between individual part numbers and associated manufacturing process data for different process steps for that part number. Rather than correlate data by hand, a user may click on a process step for a particular part number to instantly and accurately retrieve that data. Manufacturing process data may include, for example, backgrind process data, wire binding data, either in numerical or graphical form, testing parameters, packaging data, and labeling data. The database system of the present invention may be used to automatically program various process equipment in an assembly facility with appropriate process data to automatically process finished semiconductor wafers into packaged semiconductor circuits.
    Type: Grant
    Filed: May 13, 1998
    Date of Patent: July 3, 2001
    Assignee: Cirrus Logic, Inc.
    Inventors: Bernadette P. Romero, Carl H. Fong
  • Patent number: 5153507
    Abstract: A novel test die is disclosed for use in conjunction with a semiconductor assembly machine or process. The test die includes a plurality of sets of bond pads having different bond pad pitches which permits testing of those pitches with use of a single die. Bond pads suitable for array bonding and having different bond pad pitches are also disclosed. Electrical connections are provided between bond pads and permit detection of open and short circuits or other circuit defects. A staggered arrangement of bond pads permits bond pads to be packed more densely on the die. A method for fabricating a wafer having a plurality of bond pads which form a repeating pattern is given. The patterned wafer may be cut to form a test die having bond pads which are positioned to provide bond pad pitches as required by a user.
    Type: Grant
    Filed: November 16, 1990
    Date of Patent: October 6, 1992
    Assignee: VLSI Technology, Inc.
    Inventors: Carl H. Fong, William K. Shu
  • Patent number: 5061895
    Abstract: A system for detecting whether the ends of leads of a semiconductor package are less than a small predetermined distance from a predetermined plane. The system uses a structure having a planar surface and an elevated portion on the surface where the portion is provided with a number of slots equal to or greater in number than the number of leads on one side of the package. The height of the slots above the surface is substantially equal to the predetermined distance. In order to test whether the end portions of the leads deviate from coplanarity by a distance greater than the predetermined distance, the package is placed with its leads in contact with the surface with the leads facing the slots. The package is then slid towards the slots to determine whether all of the leads will slide into the corresponding slots. The lateral distance between each pair of adjacent slots matches the distance between the corresponding pair of leads.
    Type: Grant
    Filed: January 19, 1990
    Date of Patent: October 29, 1991
    Assignee: VLSI Technology, Inc.
    Inventor: Carl H. Fong