Abstract: A logic synthesis method uses a two-dimensional sizing progression for selecting gates from a cell library in designing an integrated circuit. The drive load and desired performance for each logic gate in a functional configuration for the integrated circuit may be determined. The device configuration or gate to implement the logic gate may be selected from a cell library. The selected gate has a drive load range encompassing the determined drive load and achieves a desired performance target for the logic gate. A two-dimensional sizing progression may be used to help minimize layout area, power consumption, and performance loss in implementing BiNMOS gates.

Abstract: An MOS dynamic random-access memory (RAM) realizable as a 64K RAM is disclosed. Single transistor cells employing capacitive storage are coupled to folded bit-line halves. These bit-line halves are connected to sense amplifiers employing cross-coupled transistors. Boosting means employing a variable capacitance are coupled to the bit-line halves to boost the potential on a line during reading. The capacitor associated with each of the memory cells is coupled to a potential which is greater than the power supply potential. This plate potential is substantially constant and independent of power supply variations and is internally generated. The dummy cells employed within the RAM are charged in a unique manner to a substantially constant potential which does not vary with power supply variations.