Patents by Inventor Carl M. Faulkner

Carl M. Faulkner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s)
    Patent number: 8658523
    Abstract: A metal source/drain field effect transistor is fabricated such that the source/drain regions are deposited, multilayer structures, with at least a second metal deposited on exposed surfaces of a first metal.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: February 25, 2014
    Assignee: Acorn Technologies, Inc.
    Inventors: Carl M. Faulkner, Daniel J. Connelly, Paul A. Clifton, Daniel E. Grupp
  • Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor
    Patent number: 8263467
    Abstract: Processes for forming self-aligned, deposited source/drain, insulated gate, transistors and, in particular, FETs. By depositing a source/drain in a recess such that it remains only in the recess, the source/drain can be formed self-aligned to a gate and/or a channel of such a device. For example, in one such process a gate structure of a transistor may be formed and, in a material surrounding the gate structure, a recess created so as to be aligned to an edge of the gate structure. Subsequently, a source/drain conducting material may be deposited in the recess. Such a source/drain conducting material may be deposited, in some cases, as layers, with one or more such layers being planarized following its deposition. In this way, the conducting material is kept within the boundaries of the recess.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: September 11, 2012
    Assignee: Acorn Technologies, Inc.
    Inventors: Daniel E. Grupp, Daniel J. Connelly, Paul A. Clifton, Carl M. Faulkner
  • PROCESS FOR FABRICATING A SELF-ALIGNED DEPOSITED SOURCE/DRAIN INSULATED GATE FIELD-EFFECT TRANSISTOR
    Publication number: 20110124170
    Abstract: Processes for forming self-aligned, deposited source/drain, insulated gate, transistors and, in particular, FETs. By depositing a source/drain in a recess such that it remains only in the recess, the source/drain can be formed self-aligned to a gate and/or a channel of such a device. For example, in one such process a gate structure of a transistor may be formed and, in a material surrounding the gate structure, a recess created so as to be aligned to an edge of the gate structure. Subsequently, a source/drain conducting material may be deposited in the recess. Such a source/drain conducting material may be deposited, in some cases, as layers, with one or more such layers being planarized following its deposition. In this way, the conducting material is kept within the boundaries of the recess.
    Type: Application
    Filed: February 2, 2011
    Publication date: May 26, 2011
    Inventors: Daniel E. Grupp, Daniel J. Connelly, Paul A. Clifton, Carl M. Faulkner
  • Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor
    Patent number: 7902029
    Abstract: Processes for forming self-aligned, deposited source/drain, insulated gate, transistors and, in particular, FETs. By depositing a source/drain in a recess such that it remains only in the recess, the source/drain can be formed self-aligned to a gate and/or a channel of such a device. For example, in one such process a gate structure of a transistor may be formed and, in a material surrounding the gate structure, a recess created so as to be aligned to an edge of the gate structure. Subsequently, a source/drain conducting material may be deposited in the recess. Such a source/drain conducting material may be deposited, in some cases, as layers, with one or more such layers being planarized following its deposition. In this way, the conducting material is kept within the boundaries of the recess.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: March 8, 2011
    Assignee: Acorn Technologies, Inc.
    Inventors: Daniel E. Grupp, Daniel J. Connelly, Paul A. Clifton, Carl M. Faulkner
  • METHOD FOR MAKING SEMICONDUCTOR INSULATED-GATE FIELD-EFFECT TRANSISTOR HAVING MULTILAYER DEPOSITED METAL SOURCE(S) AND/OR DRAIN(S)
    Publication number: 20110008953
    Abstract: A metal source/drain field effect transistor is fabricated such that the source/drain regions are deposited, multilayer structures, with at least a second metal deposited on exposed surfaces of a first metal.
    Type: Application
    Filed: September 9, 2010
    Publication date: January 13, 2011
    Inventors: Carl M. Faulkner, Daniel J. Connelly, Paul A. Clifton, Daniel E. Grupp
  • Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s)
    Patent number: 7816240
    Abstract: A metal source/drain field effect transistor is fabricated such that the source/drain regions are deposited, multilayer structures, with at least a second metal deposited on exposed surfaces of a first metal.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: October 19, 2010
    Assignee: Acorn Technologies, Inc.
    Inventors: Carl M. Faulkner, Daniel J. Connelly, Paul A. Clifton, Daniel E. Grupp