Abstract: Systems and methods for using dynamic actionable notifications are disclosed. The method includes: receiving, at a client device, a dynamic actionable notification associated with an event at a remote server, the dynamic actionable notification including one or more action items associated with the event; detecting user interaction with the dynamic actionable notification; retrieving current status of the one or more action items from the remote server; displaying one or more actionable graphical elements in a user interface of the dynamic actionable notification based on the retrieved current status of the one or more action items.

Abstract: The present invention concerns the field of diagnostic testing to confirm the presence of target pathogens in a test sample, typically obtained from a human or animal. The test has particular application in testing for viruses, but could include cancer cells or other particulate pathogens, including bacteria.

Abstract: A cable gland sealing member comprising: a sleeve (19) arranged to be slidably received within a passage (9) defined in a body (5) of a cable gland, the sleeve (19) arranged to receive a settable sealing material for forming a seal to a cable passing through the sleeve, wherein the sleeve (19) is defined by an annular side wall extending along an axial length; wherein an outer surface (71) of the sleeve (19) includes a tapered portion (95) such that the external diameter of the sleeve (19) widens in the tapered portion (95); and wherein the outer surface (71) of the sleeve (19) is arranged to form a seal with the cable gland body (5). A cable gland is also disclosed using such a sealing member.

Abstract: A turbine engine having a compressor section, a combustor section, a turbine section, and a rotatable drive shaft that couples a portion of the turbine section and a portion of the compressor section. A bypass conduit couples the compressor section to the turbine section while bypassing at least the combustion section. At least one particle separator is located in the turbine engine having a separator inlet that receives a bypass stream, a separator outlet that receives a reduced-particle stream flows, and a particle outlet that receives a concentrated-particle stream comprising separated particles. A conduit, fluidly coupled to the particle outlet, extends through an interior of at least one stationary vane.

Abstract: A turbine engine having a compressor section, a combustor section, a turbine section, and a rotatable drive shaft that couples a portion of the turbine section and a portion of the compressor section. A bypass conduit couples the compressor section to the turbine section while bypassing at least the combustion section. At least one particle separator is located in the turbine engine having a separator inlet that receives a bypass stream, a separator outlet that receives a reduced-particle stream flows, and a particle outlet that receives a concentrated-particle stream comprising separated particles. A conduit, fluidly coupled to the particle outlet, extends through an interior of at least one stationary vane.

Abstract: Disclosed embodiments relate to executing a vector multiplication instruction. In one example, a processor includes fetch circuitry to fetch the vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier, decode circuitry to decode the fetched instruction, execution circuitry to, on each of a plurality of corresponding pairs of fixed-sized elements of the identified first and second sources, execute the decoded instruction to generate a double-sized product of each pair of fixed-sized elements, the double-sized product being represented by at least twice a number of bits of the fixed size, and generate an unsigned fixed-sized result by rounding the most significant fixed-sized portion of the double-sized product to fit into the identified destination.

Abstract: Embodiments of systems, apparatuses, and methods for performing vector-packed controllable sine and/or cosine operations in a processor are described. For example, execution circuitry executes a decoded instruction to compute at least a real output value and an imaginary output value based on at least a cosine calculation and a sine calculation, the cosine and sine calculations each based on an index value from a packed data source operand, add the index value with an index increment value from the packed data source operand to create an updated index value, and store the real output value, the imaginary output value, and the updated index value to a packed data destination operand.

Abstract: A turbine engine having an inducer assembly. The inducer assembly includes a centrifugal separator fluidly coupled to an inducer with an inducer inlet and an inducer outlet. The centrifugal separator includes a body, an angular velocity increaser to form a concentrated-particle stream and a reduced-particle stream, a flow splitter, and an exit conduit fluidly coupled to the body to receive the reduced-particle stream and define a separator outlet.

Abstract: Disclosed embodiments relate to executing a vector multiplication instruction. In one example, a processor includes fetch circuitry to fetch the vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier, decode circuitry to decode the fetched instruction, execution circuitry to, on each of a plurality of corresponding pairs of fixed-sized elements of the identified first and second sources, execute the decoded instruction to generate a double-sized product of each pair of fixed-sized elements, the double-sized product being represented by at least twice a number of bits of the fixed size, and generate an unsigned fixed-sized result by rounding the most significant fixed-sized portion of the double-sized product to fit into the identified destination.

Abstract: Disclosed embodiments relate to executing a vector multiplication instruction. In one example, a processor includes fetch circuitry to fetch the vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier, decode circuitry to decode the fetched instruction, execution circuitry to, on each of a plurality of corresponding pairs of fixed-sized elements of the identified first and second sources, execute the decoded instruction to generate a double-sized product of each pair of fixed-sized elements, the double-sized product being represented by at least twice a number of bits of the fixed size, and generate a signed fixed-sized result by rounding the most significant fixed-sized portion of the double-sized product to fit into the identified destination.

Abstract: Disclosed embodiments relate to executing a vector unsigned multiplication and accumulation instruction. In one example, a processor includes fetch circuitry to fetch a vector unsigned multiplication and accumulation instruction having fields for an opcode, first and second source identifiers, a destination identifier, and an immediate, wherein the identified sources and destination are same-sized registers, decode circuitry to decode the fetched instruction, and execution circuitry to execute the decoded instruction, on each corresponding pair of first and second quadwords of the identified first and second sources, to: generate a sum of products of two doublewords of the first quadword and either two lower words or two upper words of the second quadword, based on the immediate, zero-extend the sum to a quadword-sized sum, and accumulate the quadword-sized sum with a previous value of a destination quadword in a same relative register position as the first and second quadwords.

Abstract: Embodiments of systems, apparatuses, and methods for performing vector-packed controllable sine and/or cosine operations in a processor are described. For example, execution circuitry executes a decoded instruction to compute at least a real output value and an imaginary output value based on at least a cosine calculation and a sine calculation, the cosine and sine calculations each based on an index value from a packed data source operand, add the index value with an index increment value from the packed data source operand to create an updated index value, and store the real output value, the imaginary output value, and the updated index value to a packed data destination operand.

Abstract: Disclosed embodiments relate to executing a vector multiplication instruction. In one example, a processor includes fetch circuitry to fetch the vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier, decode circuitry to decode the fetched instruction, execution circuitry to, on each of a plurality of corresponding pairs of fixed-sized elements of the identified first and second sources, execute the decoded instruction to generate a double-sized product of each pair of fixed-sized elements, the double-sized product being represented by at least twice a number of bits of the fixed size, and generate an unsigned fixed-sized result by rounding the most significant fixed-sized portion of the double-sized product to fit into the identified destination.

Abstract: A turbine engine having an inducer assembly. The inducer assembly includes a centrifugal separator fluidly coupled to an inducer with an inducer inlet and an inducer outlet. The centrifugal separator includes a body, an angular velocity increaser to form a concentrated-particle stream and a reduced-particle stream, a flow splitter, and an exit conduit fluidly coupled to the body to receive the reduced-particle stream and define a separator outlet.

Abstract: A turbine engine having a bypass fluid conduit coupled to the turbine section includes at least one particle separator located within the bypass fluid conduit to separate particles from a bypass fluid stream prior to the bypass stream reaching the turbine section for cooling. A centrifugal separator for removing particles from a fluid stream includes an angular velocity increaser, a particle outlet, an angular velocity decreaser downstream of the angular velocity increaser, and a bend provided between the angular velocity increaser and the angular velocity decreaser.

Abstract: Embodiments of systems, apparatuses, and methods for performing controllable sine and/or cosine operations in a processor are described. For example, execution circuitry executes a decoded instruction to compute at least a real output value and an imaginary output value based on at least a cosine calculation and a sine calculation, the cosine and sine calculations each based on an index value from a packed data source operand, add the index value with an index increment value from the packed data source operand to create an updated index value, and store the real output value, the imaginary output value, and the updated index value to a packed data destination operand.

Abstract: A centrifugal separator for removing particles from a fluid stream includes an angular velocity increaser configured to increase the angular velocity of a fluid stream, a flow splitter configured to split the fluid stream to form a concentrated-particle stream and a reduced-particle stream, and an exit conduit configured to receive the reduced-particle stream. An inducer assembly for a turbine engine includes an inducer with a flow passage having an inducer inlet and an inducer outlet in fluid communication with a turbine section of the engine, and a particle separator, which includes a particle concentrator that receives a compressed stream from a compressor section of the engine and a flow splitter. A turbine engine includes a cooling air flow circuit which supplies a fluid stream to a turbine section of the engine for cooling, a particle separator located within the cooling air flow circuit, and an inducer forming a portion of the cooling air flow circuit in fluid communication with the particle separator.

Abstract: Disclosed embodiments relate to executing a vector multiplication instruction. In one example, a processor includes fetch circuitry to fetch the vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier, decode circuitry to decode the fetched instruction, execution circuitry to, on each of a plurality of corresponding pairs of fixed-sized elements of the identified first and second sources, execute the decoded instruction to generate a double-sized product of each pair of fixed-sized elements, the double-sized product being represented by at least twice a number of bits of the fixed size, and generate a signed fixed-sized result by rounding the most significant fixed-sized portion of the double-sized product to fit into the identified destination.

Abstract: Disclosed embodiments relate to executing a vector multiplication instruction. In one example, a processor includes fetch circuitry to fetch the vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier, decode circuitry to decode the fetched instruction, execution circuitry to, on each of a plurality of corresponding pairs of fixed-sized elements of the identified first and second sources, execute the decoded instruction to generate a double-sized product of each pair of fixed-sized elements, the double-sized product being represented by at least twice a number of bits of the fixed size, and generate an unsigned fixed-sized result by rounding the most significant fixed-sized portion of the double-sized product to fit into the identified destination.

Abstract: Disclosed embodiments relate to executing a vector unsigned multiplication and accumulation instruction. In one example, a processor includes fetch circuitry to fetch a vector unsigned multiplication and accumulation instruction having fields for an opcode, first and second source identifiers, a destination identifier, and an immediate, wherein the identified sources and destination are same-sized registers, decode circuitry to decode the fetched instruction, and execution circuitry to execute the decoded instruction, on each corresponding pair of first and second quadwords of the identified first and second sources, to: generate a sum of products of two doublewords of the first quadword and either two lower words or two upper words of the second quadword, based on the immediate, zero-extend the sum to a quadword-sized sum, and accumulate the quadword-sized sum with a previous value of a destination quadword in a same relative register position as the first and second quadwords.