Patents by Inventor Carl S. Dobbs

Carl S. Dobbs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140351551
    Abstract: Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths.
    Type: Application
    Filed: May 23, 2014
    Publication date: November 27, 2014
    Applicant: COHERENT LOGIX, INCORPORATED
    Inventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, Kenneth R. Faulkner, Keith M. Bindloss, Sumeer Arya, John Mark Beardslee, David A. Gibson
  • Patent number: 8880866
    Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: November 4, 2014
    Assignee: Coherent Logix, Incorporated
    Inventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, David A. Gibson
  • Publication number: 20140173324
    Abstract: Embodiments of a synchronous digital system are disclosed that may include generation of clock and synchronization signals. Any of a plurality of available clock signals may be selected for use as a primary clock, without causing clock-induced errors in the synchronous digital system. A clock signal generated on-chip with the synchronous digital system may be automatically selected in response to detecting a condition indicating that use of a local clock may be necessary. Such conditions may include detection of tampering with the synchronous digital system. If an indication of tampering is detected, security measures may be performed.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 19, 2014
    Applicant: COHERENT LOGIX, INCORPORATED
    Inventors: Carl S. Dobbs, Michael R. Trocino, Kenneth R. Faulkner, Christopher L. Schreppel
  • Publication number: 20140167825
    Abstract: Embodiments are disclosed of a multi-chip apparatus capable of performing multi-rate synchronous communication between component chips. Each chip may receive a common clock reference signal, and may generate an internal clock signal dependent on the clock reference signal. A clock distribution tree and phase-locked loop may be used to minimize internal clock skew at I/O circuitry at the chip perimeter. Each chip may also generate an internal synchronizing signal that is phase-aligned to the received clock reference signal. Each chip may use its respective synchronizing signal to synchronize multiple clock dividers that provide software-selectable reduced-frequency clock signals to the I/O cells of the chip. In this way, the reduced-frequency clock signals of the multiple chips are edge-aligned to the low-skew internal clock signals, and phase-aligned to the common clock reference signal, allowing the I/O cells of the multiple chips to perform synchronous communication at multiple rates with low clock skew.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 19, 2014
    Applicant: COHERENT LOGIX, INCORPORATED
    Inventors: Carl S. Dobbs, Michael R. Trocino, Kenneth R. Faulkner, Christopher L. Schreppel
  • Publication number: 20140173321
    Abstract: Embodiments of a synchronous digital system are disclosed that may include generation of clock and synchronization signals. Any of a plurality of available clock signals may be selected for use as a primary clock, without causing clock-induced errors in the synchronous digital system. The clock signals may be selected automatically or programmatically. Clock generation circuitry may generate a clock signal that is initially used as the primary clock. The clock generation circuitry may be dynamically reconfigured without interrupting operation of the synchronous digital system, by first selecting another of the available clock signals for use as the primary clock.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 19, 2014
    Applicant: COHERENT LOGIX, INCORPORATED
    Inventors: Carl S. Dobbs, Michael R. Trocino, Kenneth R. Faulkner, Christopher L. Schreppel
  • Publication number: 20140173161
    Abstract: Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.
    Type: Application
    Filed: November 21, 2013
    Publication date: June 19, 2014
    Applicant: COHERENT LOGIX, INCORPORATED
    Inventors: Carl S. Dobbs, Michael R. Trocino
  • Publication number: 20140164735
    Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors, and controllers. Each processor may include a plurality of processor ports and a sync adapter. Each sync adapter may include a plurality of adapter ports. Each controller may include a plurality of controller ports, and a configuration port. The plurality of processors and the plurality of controllers may be coupled together in an interspersed arrangement, and the controllers may be distinct from the processors. Each processor may be configured to send a synchronization signal through its adapter ports to one or more controllers, and to pause execution of program instructions while waiting for a response from the one or more controllers.
    Type: Application
    Filed: October 10, 2013
    Publication date: June 12, 2014
    Applicant: COHERENT LOGIX, INCORPORATED
    Inventors: Carl S. Dobbs, Afzal M. Malik, Kenneth R. Faulkner, Michael B. Solka
  • Publication number: 20140143470
    Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.
    Type: Application
    Filed: March 8, 2013
    Publication date: May 22, 2014
    Applicant: COHERENT LOGIX, INCORPORATED
    Inventors: Carl S. Dobbs, Michael R. Trocino, Keith M. Bindloss
  • Publication number: 20140143520
    Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.
    Type: Application
    Filed: March 27, 2013
    Publication date: May 22, 2014
    Applicant: Coherent Logix, Incorporated
    Inventors: Carl S. Dobbs, Michael R. Trocino, Michael B. Solka
  • Publication number: 20130343450
    Abstract: A split architecture for encoding a video stream. A source encoder may encode a video content stream to obtain an encoded bitstream and a side information stream. The side information stream includes information characterizing rate and/or distortion estimation functions per block of the video content stream. Also, a different set of estimation functions may be included per coding mode. The encoded bitstream and side information stream may be received by a video transcoder, which transcodes the encoded bitstream to a client-requested picture resolution, according to a client-requested video format and bit rate. The side information stream allows the transcoder to efficient and compactly perform rate control for its output bitstream, which is transmitted to the client device. This split architecture may be especially useful to operators of content delivery networks.
    Type: Application
    Filed: June 11, 2013
    Publication date: December 26, 2013
    Inventors: Michael B. Solka, Michael B. Doerr, Carl S. Dobbs, Michael W. Bruns
  • Publication number: 20120137119
    Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.
    Type: Application
    Filed: October 14, 2011
    Publication date: May 31, 2012
    Inventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, David A. Gibson
  • Patent number: 5933594
    Abstract: A monitoring system is coupled to an external computer system by an interface between a data bus internal to the monitoring system and a target bus within the external computer system. Data captured by the monitoring system from the external computer system is provided in parallel to a triggering circuit and to a buffer for temporary storage. The triggering circuit identifies the occurrence of a transaction on the bus of the external computer system and generates a signal to mark a captured data block within the buffer as being characteristic of the triggering transaction. The captured data block is compared with predetermined sets of known transaction data to determine if the captured data block is consistent with the normal operation of the external computer system. A second monitoring facility is provided to perform boundary scan testing on the external computer system.
    Type: Grant
    Filed: April 23, 1997
    Date of Patent: August 3, 1999
    Inventors: Leslie T. La Joie, Eugene M. Miller, Carl S. Dobbs, Michael B. Solka
  • Patent number: 5630048
    Abstract: A monitoring system is coupled to an external computer system by an interface between a data bus internal to the monitoring system and a target bus within the external computer system. Data captured by the monitoring system from the external computer system is provided in parallel to a triggering circuit and to a buffer for temporary storage, The triggering circuit identifies the occurrence of a transaction on the bus of the external computer system and generates a signal to mark a captured data block within the buffer as being characteristic of the triggering transaction. The captured data block is compared with predetermined sets of known transaction data to determine if the captured data block is consistent with the normal operation of the external computer system. A second monitoring facility is provided to perform boundary scan testing on the external computer system.
    Type: Grant
    Filed: May 19, 1994
    Date of Patent: May 13, 1997
    Inventors: Leslie T. La Joie, Eugene M. Miller, Carl S. Dobbs, Michael B. Solka
  • Patent number: 5173617
    Abstract: A digital phase lock loop that does not depend on a voltage controlled oscillator (VCO) for phase locking. A phase detector (PD), terminated with a latch, controls an up/down counter that programs an increase/decrease of delay on the delay line. The tapped output of the delay line goes through a two phase generator which in turn feeds back to the PD for comparison with the reference clock. This process is repeated until phase locking is obtained.
    Type: Grant
    Filed: August 10, 1989
    Date of Patent: December 22, 1992
    Assignee: Motorola, Inc.
    Inventors: Mitchell Alsup, Carl S. Dobbs, Yung Wu, Claude Moughanni, Elie I. Haddad